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Full text of "dec :: dectape :: DEC-08-H3DA-D TC08 Jun70"

Qigjtal Equipment Corporation nHHHiiHii 

Maynard, Massachusetts UUUUUUU 



PDP-8 
Maintenance Manual 



TC08 



DECtape Controller 



DEC-08-H3DA-D 



PDP-8 

TC08 

DECTAPE CONTROLLER 

MAINTENANCE MANUAL 



DIGITAL EQUIPMENT CORPORATION • MAYNARD, MASSACHUSETTS 



hf Printing June 1970 



Copyright © 1970 by Digital Equipment- Corporation 



The material in this manual is for informa- 
tion purposes and is subject to change with- 
out notice. 



The following are trademarks of Digital Equipment 
Corporation, Maynard, Massachusetts: 



DEC 


PDP 


FLIP CHIP 


FOCAL 


DIGITAL 


COMPUTER LAB 



euNltNib 



Page 



CHAPTER 1 INTRODUCTION 



1.1 The Type TC08 and TC08N Conlrollers 1-1 

1.2 The TU55 a nd TU56 Tra nsports 1 - 1 

1.3 Installation and Environmental Requirements 1-3 

CHAPTER 2 THEORY OF OPERATION 

2. 1 DECtope Recording Format 2-1 

2.2 DECtape Data Format 2-2 
2.2.1 Block Lengths 2-4 

2.3 Bidirectional Reading and Writing 2-4 

2.4 The TC08 Block Diagram 2-7 

2.4.1 The Data Transfer Section 2-8 

2.4.2 The Control Section 2-10 

2.5 Functions and Flags of the Control Section 2-11 

2.5.1 Functions of the Status A Register 2-11 

2.5.2 Errors and Flags of the Status B Register 2-13 

2.6 Programming DECtape 2-14 

2.6.1 Example 1: Rewind Tape 2-15 

2.6.2 Example 2: Find a Block 2-16 

2.6.3 Summary of TC08 Timing Data 2-17 

2.7 TC08 Operator Controls and Indicators 2-18 

CHAPTER 3 TC08 - TC08N LOGICAL OPERATION 

3.1 A Review of Magnetic Tape Recording 3-1 

3.1.1 Magnetic Recording in General 3-1 

3.1.2 The DECtape ReadA^rite Electronics 3-2 

3.1.3 The DECtape Recording Technique 3-3 

3.2 The DECtape System 3-5 
3.2.1 The DECtape Controller 3-5 

3.3 The TC08 System Timing 3-24 

3.3.1 Write Timing and Mark Track 3-24 

3.3.2 Search and Write Data or Write All 3-24 



CONTENTS (Cont) 



Page 



3.3.3 Read Data and Read All 3-26 

3.4 Move 3-26 

3.5 TC08 Versus TC08N 3-26 

CHAPTER 4 INSTALLATION 

4. 1 Unpacking 4-1 

4.1.1 Hardware 4-1 

4.1.2 Software 4-1 

4.1.3 Inspection 4-5 

4.2 Space and Environmental Requirements 4-5 

4.2.1 Space Requirements 4-5 

4.2.2 Environmental Requirements 4-5 

4.3 Power Requirements 4-6 
4.3.1 Power Supplies 4-6 

4.4 TC08 Cabling 4-6 

4.4. 1 Cabling the TC08 to the Computer 4-6 

4.4.2 Cabling the TC08 to the TU55 or TU56 Transports 4-6 

4.4.3 Cabling the Display Panel 4-7 

4.5 Final Checkout 4-8 

CHAPTER 5 CHECKOUT AND AAAINTENANCE 

5. 1 The TC08 Maintenance Concept 5-1 

5.2 Troubleshooting the TC08 5-1 

5.3 TC08 Assembly 5-2 

5.3.1 Equipment 5-2 

5.3.2 Procedure 5-3 

5.4 TC08 Preliminary Checkout and Calibration 5-4 

5.5 TC08 Diagnostic Testing 5-6 

5.5.1 Diagnostics 5-6 

5.5.2 Testing the Mark Track Decoder 5-7 

5.6 DECtape Preventive Maintenance 5-7 

5.6.1 Handling Magnetic Tape 5-7 

5.6.2 Cleaning DECtape Reels 5-8 



IV 



N-V^l N I 1_ IN I O V^N^UMI/ 



Page 



5.6.3 Storing Tapes ^-9 

5.6.4 Physical Distortion 5-9 

5.6.5 Accidental Erasure or Saturation 5-9 

5.6.6 Head Care and Head Life 5-10 
5.7 Module and Accessory Warranties 5-10 

5.7.1 Type B, R, W, M, K and A Modules 5-10 

5.7.2 System Modules 5-11 

5.7.3 Shipping 5-11 

5.7.4 Systems 5-11 

5.7.5 Other Warranty Conditions 5-12 
o.o service roiicy 5-12 
5.9 Spare Parts 5-12 

CHAPTER 6 TC08, TC08/N MODULES 

6.1 DEC Logic 6-1 

6.2 Measurement Definitions 6-3 

6.3 Loading 6-3 

6.4 Module Characteristics 6-3 

6.4.1 G775 Connector Card 6-3 

6.4.2 G879 Transports Detector Module 6-3 

6.4.3 0888 Manchester Reader/Writer Module 6-4 

6.4.4 M 100 Bus Data Interface 6-5 

6.4.5 M102 Device Selector 6-7 

6.4.6 M228 Mark Track Decoder 6-8 

6.4.7 W032 Connector 6-9 

6.4.8 716 Indicator Supply 6-9 

6.4.9 M623 Bus Driver 6-9 

6.4.10 M633 Negative Bus Driver 6-10 

CHAPTER 7 DOCUMENTATION 7-1 



ILLUSTRATIONS 
Figure No. Title 

1-1 Type TU55 DECtape Transport 

1 O T. Tl ICZ niC^i__,_ X.._^-„_..jL 

I -.£. ' yp** iUw)u u'tNwrupe ironsporr 

2-1 DECtape Heads and Tape Channels 

2-2 DECtape Data Blocks 

2-3 DECtape Data Format 

2-4 Bidirectional Reading and Writing 

2-5 TC08 Data Transfer Section 

2-6 TC08 Control Section 

2-7 The Indicator Panel 

3-1 Simplified Diagram of the Magnetic 
Recording Process 

3-2 DECtape Read/Write Electronics and 
Waveforms 

3-3 The TC08 DECtape Controller Block 
Diagram 

3-4 Command Register 

3-5a Command Register Timing with PDP-8/L 

3-5b Command Register Timing with PDP-8 

3-5c Command Register Timing with PDP-8/l 

3-6 Timing Generator 

3-7 The Counters 

3-8 The Window Register and State Generator 

3-9 Data Buffer 

3-10 The Longitudinal Parity Buffer 

3-11 The I/O Control 

3-12 The I/O Control Timing 

3-13 The DECtape Flag 

3-14 The Write Enable Flag 

3-15 Status B Logic of the Error Flags (2 Sheets) 

3-16 Write Timing and Mark Track Timing 
Diagram 

3-17 Timing Diagram for Driving Search Write 
Data or Write All 

3-18 Timing Diagram for Read Data and Read A I 

4- la H950 Frame 

4- lb H950 Frame, Dimension Diagram 



Art No. 


Page 


N96-074n 


1-2 


oy -ouo-z-o 


1-2 


08-0441 


2-2 


08-0453 


2-3 


08-0465 


2-5 


08-0442 


2-6 


08-0439 


2-8 


08-0440 


2-9 


69-338-12-1 


2-18 


08-0458 


3-2 


08-0451 


3-4 


08-0430 


3-6 


08-0443 


3-7 


08-0433 


3-9 


08-0434 


3-9 


08-0435 


3-9 


08-0449 


3-n 


08-0448 


3-12 


08-0447 


3-13 


08-0445 


3-16 


08-0446 


3-17 


08-0444 


3-18 


08-0466 


3-19 


08-0432 


3-20 


08-0450 


3-20 


08-0459 


3-22 


04-0436 


3-25 


08-0438 


3-27 


08-0437 


3-29 




4-2 


08-0457 


4-3 





ILLUSTRATIONS (Cont) 






Figure No. 


Titie 


Art No. 


Page 


4-2 


DECtape System in Cabinet 


N96-074n 


4-4 


4-3 


DECtape Cabies 


08-0452 


4-7 


6-1 


Voltage Spectrum of Negative Logic 
Systems 


08-0462 


6-1 


6-2 


Voltage Spectrum of TTL Logic 


08-0463 


6-2 


6-3 


Voltage Spectrum for Positive PDP-8 
I/O Bus Logic 


08-0464 


6-2 


6-4 


The Gll^ Connector Card Logic Symbol 


08-0460 


6-3 


6-5 


The G879 Transport Detector Module 


08-0456 


6-4 


6-6 


G879 Application 


08-0454 


6-4 


6-7 


The G888 Reader/Writer 


08-0455 


6-4 


6-8 


The Ml 00 Bus Data Interface Module, 
Logic Diagram 


08-0428 


6-6 


6-9 


The M102 Device Selector 


08-0431 


6-7 


6-10 


M623 Driver 


08-0426 


6-10 


6-n 


M633 Negative Bus Driver 


08-0427 


6-11 



TABLES 

2-1 Complements 2-7 

2-2 Status A-bit Assignments 2-10 

2-3 DECtape Instructions 2-11 

2-4 The TC08 Indicator Panel 2-18 

3-1 Mark Track and Window Codes 3-15 

3-2 The Error Flags 3-21 

4-1 TC08 Software 4-5 

4-2 DECtape Cables 4-5 

4-3 TC08 or TC08N to the PDP-8, 8/l, or 8/L Cabling 4-6 

4-4 Cabling Between the Controller and Transports 4-7 

4-5 Cabling Between the Controller and Display Panel 4-8 

5-1 Voltage Test Points 5-3 

5-2 The Indicator Cables 5-3 

5-3 Computer and Transport Cables 5-4 

5-4 The Switch Register Bits 5-5 

5-5 Visual Inspection Checklist 5-8 

5-6 Recommended TC08, TC08/N Spares 5-12 

7-1 TC08, TC08/N Signals 7-1 

7-2 Engineering Drawings 1-1 

vii 



PREFACE 



This manual has been written to explain the operation of the TC08 DECtape controller and to detail the funda- 
mentals of its design. It is suitable for programmers familiar with the PDP-8 computer and practicing engineers 
experienced in digital systems. It assumes that the reader is familiar with the following publications: 

TU55 DECtape 55 DEC-00-HZTA-D 
PDP-8 User's Handbook 
Logic Handbook C-105 

The manual is divided into seven chapters. 

Chapter 1 introduces DECtape, the TC08 Controller, and the TU55 and TU56 DECtape Transports. 

Chapter 2 covers the DECtape recording format, the system block diagram, and its instruction set. This chapter 
provides data required for a user or programmer. 

Chapter 3 covers the basic architecture of the TC08. Detailed block diagrams, prints, and timing charts are 
presented with narrative. 

Chapter 4 provides instructions for installing the TC08, and Chapter 5 outlines maintenance procedures. 

Chapter 6 describes the DEC modules used in the TC08 but not explained in the Logic Handbook. 

Chapter 7 contains the technical documentation for the TC08. 




oooo 



DOOO 









, i-tiK^, 









>*i« 






TC08 DECtape Confroiler 



CHAPTER 1 
INTRODUCTION 

DECtape is a 10-track digital magnetic tape recording system designed and produced by Digital Equipment 
Corporation to store large amounts of digital information for computers. The system is divided into distinct 
units - a controller and number of transports. Each family of DEC computers uses its own DECtape controller to 
drive up to 8 DECtape transports. The PDP-8 family uses the TC08 or the TC08N controllers for its positive 
logic or negative logic PDP-8 computers, respectively. These controllers will operate either the TU55 or the 
TU56 tape transports (see Figures 1-1 and 1-2). 

This manual explains the operation of the TC08 and TC08N controllers for the user, and details the fundamentals 
of their logic design as a guide to maintenance personnel , 

1.1 THE TYPE TC08 AND TC08N CONTROLLERS 

The TC08 and TC08N are the primary controls for up to 8 TU55 or 4 TU56 tape transports. These controls 
handle data and command signals for the PDP-8 family of computers through their l/O Bus or 3-cycle data break, 
and supply read/write circuitry, block format detection, and error detection logic to each transport. The TC08 
is used with computers in the PDP-8 series which have positive logic l/O systems, and the TC08N is used with 
computers in the PDP-8 series which have negative logic l/O systems. The differences between the two controls 
are elementary; unless otherwise specified, any description of one applies to the other. 

1 .2 THE TU55 AND TU56 TRANSPORTS 

Each transport contains motor, motor drivers, tape heads, and the logic necessary for selection, motion control, 
and data transfer. 

The TU55 transport consists of one tape drive capable of handling 260-foot reels of 3/4-inch, 1-mil magnetic 
tape. The bits are recorded at a density of 350 ± 55 bits per track inch. The tape moves at a speed of 93 ± 12 
inches per second; with 3 data tracks available, an effective information transfer rate of 350 x 93 x 3 = 97650 
bits per second is achieved. Individual 12-bit words which are assembled by the TC08 control unit arrive at the 
computer approximately every 132 microseconds. The computer must accept this data in 20 microseconds. Data 
is stored in individually addressable blocks, which can be specified by the user and written into or read from in 
either direction of tape motion. Up to 190,000 12-bit words con be stored on a reel of tape. 

1-1 




Figure 1-1 Type TU55 DECfape Transport 




Figure 1-2 Type TU56 DECtape Transport 
1-2 



1 .3 INSTALLATION AND ENVIRONMENTAL REQUIREMENTS 

The TC08 controllers and both types of transports will mount in standard 19-inch cabinets. Cables from the 
PDP-8 l/O Bus and the three-cycle data break facility are connected to the controller, and two cables are 
chained from the controller through each transport to supply control and data information there. The system 
will operate in a temperature range of 60°F to 80°F at relative humidities of from 40% to 60%. These 
restrictions are due to the magnetic tape itself. 

Chapter 4 describes installation procedures in detail . 



1-3 



CHAPTER 2 
THEORY OF OPERATION 

The purpose of Chapter 2 is to describe the operational nature of DECtape. It covers the recording format for 
data and control information, outlines and explains the system block diagram, and presents the instruction set 
used by the PDP-8 computer to control and communicate with the TC08 and the TU55 or TU56 transports. 

2,1 DECTAPE RECORDING FORMAT 

Two of the features of DECtape mentioned in Chapter 1, individually addressable blocks and bidirectional 
reading and writing, stem from the recording format used by DECtape. This format affects not only data, but 
rilcr* * f^^tructions tellin*^ D^Ctaoe what to do wi**! tHe dato 

Both the data and the instructions are stored in or read from the magnetic tape through read/write heads which 
magnetize the tape in one of two directions to represent a "0" or a "1", and read the same information back. 
There are ten such heads distributed along the width of the tape, each head covering a narrow path called a 
tape track or channel . Figure 2-1 shows a tape stretched over the ten heads to indicate how the width is 
divided into ten tracks. 

The ten tracks and heads are divided functionally into five pairs. The two outside tracks are called timing 
channels. On these tracks signals are prerecorded at a fixed frequency, and used to strobe information into or 
from the other tracks. The tape controller synchronizes on these pulses. The two tracks next to the timing 
channels are called mark tracks. These record the instructions which tell the TC08 controller where the tape is 
and what type of data is stored In the associated information tracks. The information or data tracks are placed 
in the middle of the tape where the effect of skew is at a minimum. Like the timing and mark tracks, the data 
channels are paired up. 

The reliability of this recording/reading system is high because the 10 tracks are divided into five pairs of 
counterparts. That is, corresponding heads for each track are wired in series and record and write the same 
information. During reading, the analog sum of the two heads is used to detect the correct value of the bit. 
Therefore a bit cannot be misread until the noise on the tape is sufficient to change the polarity of the sum of 
the signals being read. During writing, corresponding heads record the same information. 



2-1 



3/4 INCH MAGNETIC TAPE 




NOTE THAT EACH PAIR OF 
HEADS IS ACTUALLY WIRED 
IN SERIES.AND TWO WIRES 
ARE RUN TO A DIFFERENTIAL 
AMPLIFIER. FOR SIMPLICITY 
A SINGLE WIRE FOR EACH 
PAIR IS SHOWN HERE. 



DEC TAPE HEADS 



08-0441 



Figure 2-1 DECtape Heads and Tape Channels 

In summary, the five pairs of tracks consist of the timing tracks used to strobe other tracks, the mark tracks 
which store instructions, and three data tracks. A 12-bit PDP-8 word, then, uses four slots of 3 data bits each. 

2.2 DECTAPE DATA FORMAT 

A 260-foot reel of DECtape, shown in Figure 2-2, is divided into three zones; two end zones and the recording 
zone. The end zones, about 10 feet long, are used to wind the tape around the heads and onto the take-up 
reel . They never contain data . 

The recording zone is divided into blocks. Each block will store a specified number of data words and several 
control words. The number of data words a block will store is determined when the tape is preformatted with its 
timing and mark track. In standard format, 1474,-. blocks, each with 129..^ 12-bit words, can be stored on a 
260-ft reel . The total length of the tape is equivalent to 884,736 data lines which can be divided into any num- 
ber of blocks up to 4096. 



2-2 



BLOCK 



/ 



^ 



BLOCK 
NUMBER 
12 BITS 



PARITY 
BLOCK 
6 BITS 



DATA BLOCK 
129 10-12 BIT WORDS 



PARITY i BLOCK 
BLOCK I NUMBER 
6 BITS ! 12 BITS 



^ 



1*1 Oft. 



RECORDING ZONE 
(240 ft.) 



-^♦lOft.-*^ 



END 
ZONE 


BLOCK 


BLOCK 


BLOCK 


BLOCK 


1) 


BLOCK 


BLOCK 


BLOCK 


BLOCK 


END 
ZONE 


\ 


b 




















^ 



Figure 2-2 DECtape Data Blocks 



Recording information on tape in blocks permits digital data to be partitioned into blocks of words which are 
interrelated and at the same time reduces the amount of storage area which would be needed to address individual words . 

A simple example of such a partition Is the coding of a program. A program can be stored and retrieved from 
magnetic tape in a single block format because it is not necessary to be able to retrieve only a subgroup of the 
coding. The computer usually wants the complete program, or none of It. It is necessary, however, to be able 
to identify and retrieve different programs, since they may not be related. They would be stored in different 
blocks of tape. 

The data stored on a DECtape reel is organized into such blocks of data, with the following advantages: 

a. Each block is numbered, and can be Identified by the computer during a random search. 

b. Errors can be detected within a block, using serial parity checking. 

c. A block can be read or written while the tape is travelling In either direction. 

A block is identified by a number recorded during tape formatting on the data tracks just before and after the 
area where data is stored In the block. This number is recorded at either end of a block so that it can be read 
from either direction. 

Errors in reading or writing data are detected by calculating the parity of each data track as the block is written, 
and recording the checksum at the end of the block. When the block is read, the same parity checksum is cal- 
culated, and the result Is compared with the original . If they compare favorably, the transfer Is assumed to be 
valid. Otherwise, an error has occurred and the computer is notified. Since reading and writing must occur In 
either direction, the checksum must be recorded at each end of the block. 



2-3 



The average access time to any block is decreased if a block can be written or read from either direction. This 
is facilitated by writing the block number and leaving room for a parity checksum at either end of each block. 
However, there are further complications if a block is read in a direction opposite to the one from which it was 
written. The complications are covered in the next section. 

The purpose of the pre-recorded mark track now becomes apparent . The code of this track identifies the infor- 
mation of the three data tracks as being a block number, a parity checksum, or data proper. In each case, the 
controller responds appropriately by either transferring the block number to the computer for identification, 
calculating the checksum, or transferring the data. The mark track must also perform several other functions, 
detecting such things as the end of tape zones, the beginning and end of blocks, and no operation (delaying) 
conditions. The various functions and their codes are summarized in Figure 2-3. Note that data is stored in 
cells which are 6 lines and 3x6 = 18 bits long. This will affect the acceptable length of a block, since it must 
be in increments of cells divisible by 12. 

2.2.1 Block Lengths 

DEC provides a program called the DECtape formatter which is used to write the timing track, mark track, and 
block numbers onto a reel of DECtape. The formatter will allow the user to specify the number of data words he 
wants in each block within the constraints of a given formula. The formatter is described in TC08 DECtape 
Formatter, DEC-08-EUFA-D. 

2.3 BIDIRECTIONAL READING AND WRITING 

The freedom to read or write on DECtape in either direction raises some interesting problems. For example, if a 
bit is written as a 1 while the tape is travelling from left to right, then it would be read as such when the tape 
is travelling in the same direction during the read operation. Otherwise, that same bit is seen as a zero. 
Further, a complete word or mark track instruction read one way would be assembled in reverse order when read 
the other. Figure 2-4 illustrates this process. Here, a 42_ read from left to right becomes a 56p if read in the 
reverse direction. 

However, the problem is less complicated than it appears. 56 represents the obverse complement of 42o; 
every number has one such counterpart, as shown in Table 2-1 . 

Data read into the computer in the opposite direction from that in which it was recorded is then in its obverse 
complement form. It can be reconverted by means of a simple algorithm. It is necessary only that the user be 
aware of how the data was recorded and read . 



2-4 



[• — CELL H 



REV END 
MARK 



55 



INTERBLOCK FORWARD REVERSE GUARD 
SYNC BLOCK MARK MARK 



25 



26 



32 



LOCK 
MARK 



10 



REVERSE REVERSE REVERSE DATA 

PCC MARK FINAL MARK PREFINAL MARK MARK 



10 



10 



10 



70 



DATA 
MARK 



70 



PREFINAL 
MARK 



73 



FINAL 
MARK 



73 



PCC REVERSE GUARD REVERSE INTERBLOCK END 

MARK LOCK MARK MARK BLOCK MARK SYNC MARK 



73 



73 



51 



45 



25 



22 



101 101 



10110 
BLOCK 
NUMBER 
RECORDED 
HERE 



00 1 000 



00 1 000 



00 100 



111000 



1110 11 
PARITY 
STORED 
HERE 



101001 



100 101 



-► DIRECTION OF MOTION 



DATA STORED HERE 



10 10 1 



TIMING TRACK 
MARK TRACK 



DATA TRACKS 



MAGNETIC 
TAPE 



Code Name 

55 REVERSE END MARK 



25 



26 



32 
10 

10 



]0 
10 



INTERBLOCK SYNC 



FORWARD BLOCK MARK 



REVERSE GUARD MARK 
LOCK MARK 

REVERSE PCC MARK 



REVERSE FINAL MARK 
REVERSE PREFNAL MARK 



Function 

This code identifies the end zone that the tape transport 
is leaving as it moves toward the data block zone. No 
action is taken by the controller. 

Code 25 is another no-op code which lies between blocks 
and for several feet on the inside of the end zones. It 
allows for turnaround time when reading the first and last 
block, and is used by the controller to synchronize its 
timing logic between blocks. 

In this cell the number assigned the block by the for- 
matter is stored. When the computer is searching for a 
block, it transfers this number into memory and examines 
it. When code 26 is decoded by the controller, it knows 
that the block number is ready and informs the computer. 

These two cells are no-op conditions which give the 
computer time to decide on what to do with the block it 
has identified . 

This is the last cell before a data cell . It is used to ini- 
tiate the parity checksum logic. If the computer were 
writing, the first 12-bit word to be written is transferred 
to the controller during this cell, and every 4 lines 
thereafter. 

These two codes indicate the first and second data words 
respectively . Otherwise they have no special significance . 



Code Name 

70 DATA MARK 



73 


PREFINAL MARK 


73 


FINAL MARK 


73 


PCC MARK 



73 
51 
45 

25 
22 



REVERSE LOCK MARK 
GUARD MARK 
REVERSE BLOCK MARK 

INTERBLOCK SYNC 
END MARK 



Function 

The 70 code simply indicates that a data word is con- 
tained in the data tracks. The controller logic contin- 
ually checks to see that the mark track is coded. 

These codes indicate that the last two words of data are 
being transferred. 

The parity checksum which was being calculated during 
the transfers is either deposited here during writing or 
compared during reading. If there is an error, the com- 
puter is notified at this point. 

These are no-op spaces which become useful when the 
tape is operating in the reverse direction. 

The block number is stored here to be picked up by the 
computer when the tape is traveling in the reverse 
direction. 

Has the same function as its counterpart at the begin- 
ning of the tape. 

When this code comes up, the program is informed that 
it has just run out of tape and that it had better do some- 
thing about it! Note that it is the obverse complement 
of 55, 



Figure 2-3 DECtape Data Format 



2-5 



TIME 


DATA READ IN SAME DIRECTION 
AS RECORDED 


DATA READ IN OPPOSITE DIRECTION 
FROM THAT RECORDED 


TIME 


1 
2 

3 

4 

5 
6 


TAPE 

—¥■ DIRECTION OF TAPE MOTION 

\ ONE CHANNEL 10 10 

DATA -^ /—^ 

1 K-HEAD 


] 


TAPE 
DIRECTION OF TAPE MOTION < 

} ONE CHANNEL 10 10 j 

HEAD-H^ ^°^^^ 


1 
2 

3 

4 

5 
6 




1 "I 


L 


1 T 




















SHIFT REGISTER 




















SHIFT REGISTER 










t_ NOTE THAT THE 1 READ BACKWARDS 
BECOMES A ZERO (FLUX REVERSES) 


— 


-^ 


^ 


\ 10 10 


J 1 1 i 




^ 




, a 


1 



















^ 


1 

































— 




<- 


1 1 


J 


10 10 j 

Pi 






1 "-T-' 




1 •— I-* 





1 
















1 


1 




























-► 




L 


1 10 

, 6 


_ 


L 


10 10 j 

1 U-l 








1 













1 


1 


1 

























*- 


^ 


5 10 10 

Pi 


J 


j 10 10 

p 




1 --r- 




1 >-,-' 











1 










u. 





1 


1 


1 






















— 


— 


j 10 10 


J 


f 10 10 } 

p 




1 ^r- 




1 —I— 


1 











1 







1 





1 


1 


1 









428 






568 





ns-n^^9 



Figure 2-4 Bidirectional Reading and Writing 



2-6 



Comoiemenfs 



Number (Octal) 


Obverse Complement (Octal) 





7 


1 


3 


2 


5 


3 


1 


4 


6 


5 


2 


6 


4 


7 






There is a problem with the information on the mark track, however; the mark track must identify data or con- 
trol words no matter which way the tape travels, and these codes should read the same. Fortunately, some 
codes map into themselves as obverse complement. (For example, the obverse complement of 70 is 70 itself.) 
Such codes are used by the mark track to avoid the obverse problem. Note from Figure 2-3 that if the tape 
were travelling in the opposite direction, and all mark track codes were transferred to their obverse complement, 
the mark track read head would see exactly the same series of codes. 

By using these principles, DECtape has been designed to be read or written in either direction, in randomly 
selected data blocks at high reliability. The programmer must be aware of how data was recorded in order to 
ensure that he has the data or its obverse complement; the TC08 controller handles all other problems. 

A more detailed explanation of how DECtape actually records, and the nature of the instructions in the mark 
track will be covered in later chapters. This information is not needed to use DECtape. 



2.4 THE TC08 BLOCK DIAGRAM 

The TC08 is studied in two parts; the data transfer section and the control section, shown in Figures 2-5 and 2-6. 
Through the data transfer logic, the TC08 manipulates data in twelve-bit bytes between computer memory and its 
data buffer, using the three-cycle data break facility. Through the control section, the software operating sys- 
tem initializes the controller by selecting the transport with which it wishes to deal, the direction of tape motion 
of the transport, the function it is to perform, and the mode in which it will operate. The control also monitors 
the system for errors, and sets up interrupt flags to notify the computer when either an error has occurred or the 
function specified is finished. 



2-7 



DATA CHANNEL 1 — ♦ 



I DATA REGISTER— I [-WRITE BUFFER-] pl-PB REGISTER-] 






DATA CHANNEL 2 — • 







♦ 






♦ 






















10 


7 


4 


1 




t 




4 


1 










» 












" 




t " 



j-^—i 



DATA CHANNEL 3 — ♦ 







11 


8 


5 


2 




2 




5 


^ 


n 








'^ 1 




» 












w 




t ' 



WINDOW 
(INSTRUCTION REGISTER) 



TIMING TRACK- 



MARK TRACK »" 98 7654321 



TC08 DATA CONTROL LOGIC 



SHIFT 



THREE CYCLE DATA 

BREAK CONTROL 

LOGIC 



DATA ADD 00 THRU 
DATA ADD 1 1 



CONTROL SIGNALS 
lOP PULSES 



DATA 00 THRU 
DATA 11 { TO MB ) 

BMB 00 THRU 
BMB 11 (FROM MB) 



STATUS REGISTER B 
BITS 6,7,8 



TRANSFER 
REQUEST (IN, OUT) 



*■ SET DECTAPE FLAG 
STATUS A REGISTER 

Figure 2-5 TC08 Data Transfer Section 



2.4.1 The Data Transfer Section 

The data transfer section is not directly available to the software operating system; once the controller has been 
initiated, the data section detects the position of the tape and carries out the specified operation. If the opera- 
tion is to read data from the computer and store it on tape, then a three-cycle data break request is initiated 
and the correct block of words is transferred to the data buffer when the window register detects that block posi- 
tion on the tape. At the same time, the data section calculates the parity checksum in the longitudinal parity 
buffer, so that this sum can be checked at the end of the block. 

If a write operation was specified, then the window register notifies the control when the first data word of the 
block is ready. This word is assembled into the data buffer; when the data buffer is full, the control requests 
that its contents be transferred to computer memory through the three-cycle data channel . Simultaneously, the 
parity checksum is calculated and deposited at the end of the block. 

During a read operation, the computer must take the word in about 30 jjs. During a write operation, the comput- 
er must supply a word in 16 ps. 



2-8 



STATUS 
REGISTER 
A BITS 


FUNCTION 


0-2 


DECODED TO SELECT ONE OF EIGHT POSSIBLE 
TRANSPORTS 


3-4 


DETERMINES FORWARD, REVERSE STOP OR 
START MOTION 


5 


NORMAL OR CONTINUOUS MODE 


6,7,8 


DECODED TO SELECT ONE OF EIGHT POSSIBLE 

FUNCTIONS INCLUDING READ OR WRITE 


9 


ENABLES DECTAPE FLAG TO CAUSE PI 
WHEN SET 


10 


0- CLEARS ALL ERRORS FLAGS 
1- NOTHING 


11 


0- CLEAR DECTAPE FLAG 
1- NOTHING 



STATUS 
KtbiS 1 t.H 

B BITS 


FUNCT!0^4 





SET IF ANY ONE OF THE ERRORS DESCRIBED BY 
STATUS B BITS 1-5 OCCURS 


1 


MARK TRACK ERROR 


2 


END OF TAPE ERROR 


3 


SELECT ERROR 


4 
5 


PARITY ERROR 
TIMING ERROR 


6,7,8 


MEMORY FIELD SET FROM THE ACCUMULATOR 


9,10 


NOT USED 


11 


DECTAPE FLAG SET AT THE COMPLETION OF 
A SELECTED FUNCTION 



note: 



A BIT OF EACH STATUS REGISTER IS SET BY ITS 
CORRESPONDING BIT IN THE ACCUMULATOR WHEN 
THE PROPER LOAD STATUS lOT IS ISSUED. 
SIMILARLY, WHEN THE READ STATUS lOT IS ISSUED, 
EACH BIT OF THE STATUS REGISTER ADDRESSED 
IS READ INTO ITS CORRESPONDING ACCUMULATOR BIT. 



STATUS REGISTER 
A 



STATUS REGISTER 
B 






1 


2 


3 


4 


5 


6 


7 


8 


9 


10 


11 



Ji. 






1 


2 


3 


4 


5 


6 


7 


8 


9 


10 


" 



SET ERROR FLAGS 
(FROM CONTROLS) 



FROM TC08 _ 
CONTROL LOGIC 



lOP 1 , 2 , 4 



BMB 03-08 



SAC 00 
TO BAG 11 



FROM 
ACCUMULATOR 



AC 00 TO AC11 



TO 
ACCUMULATOR 



DEVICE 
SELECT 

LOGIC 
I/O 
CONTROL 



TDT K7K1 



lOT 6762 



lOT 6764 



rOT 6771 



lOT 6772 



lOT 6774 



RECEIVE LOGIC 

FROM 
ACCUMULATOR 



TRANSMIT LOGIC 

TO 
ACCUMULATOR 



READ STATUS A 
CLEAR STATUS A 
XOR STATUS A 

SKIP ON ERROR OR DECTAPE FLAG 
READ STATUS B 
LOAD STATUS B 



BAC0(2I- 11 



SET DECTAPE 

FLAG 

(FROM 

CONTROL) 



BAC 06- 
SAC 08 



IM 00-11 



Figure 2-6 TC08 Control Section 



2-9 



These operations presumed that the software operating system had initiated its word count (location 7754) and 
current address (location 77^5) to the block length and first address (minus one) to or from which the data was 
to be transferred . 



2.4.2 The Control Section 

The control section consists of two registers, status A and status B, and the device select logic. Status A regis- 
ter accepts commands, and status B reports the system status. The device select logic is used to clear, load, 
test, or read these registers under lOT control from the computer. Figure 2-6 summarizes the function of each 
bit in these registers. Table 2-2 expands on the figure, and Table 2-3 lists the lOT instructions and explains the 
use of each . 

Table 2-2 
Status A-bit Assignments 



Function 


Bit 


Conditions 


Transport Unit Select 


0-2 


Octal Code Unit 


000 8 or 






001 1 






010 2 






Oil 3 






100 4 






101 5 






110 6 






111 7 


Motion 


3 


= Forward (FWD) 

1 = Reverse (REV) 




4 


= Stop motion (STOP) 

1 = Start motion (GO) 


Mode 


5 


= Normal mode (NM) 

1 = Continuous mode (CM) 


Function 


6,7,8 


Code Operation 

000 Move 

001 Search 
010 Read data 
Oil Read all 

100 Write data 

101 Write all 

110 Write timing 

111 Unused (causes select 
error) 


Enable the Interrupt 


9 


1 ^ Enable DECtape control flag (DTCF) to 
the program interrupt 


Error flag 


10 


= Clear all error flags 

1 = Error flags undisturbed 


DECtape flag 


n 


= Clear DECtape flag 






1 = DECtape flag undisturbed 



2-10 



Table 2-3 
DECrape Insfrucflons 



Mnemonic 



DTRA (read status register A) 



DTCA (clear status register A) 



DTXA (load status register A) 



Octal 
Code 

6761 
6762 
6764 



DTSF (skip on flags) 



DTRB (read status register B) 



6771 



6772 



DTLB (load memory field of 
status register B) 



6774 



Operation 



The contents of status register A are loaded into the 
accumulator by an OR transfer. 

Status register A is cleared. The DECtape and error 
flags are undisturbed. 

Bits - 9 of the status register are complemented if 
their corresponding bits in the accumulator are set to a 
1 . In other words, the exclusive OR between corres- 
Dondspa b'^'S •<: loaded intr> th^ <;tDfi!<; A r^^ni^fer. and 
bits 10 and 11 of the accumulator are sampled to control 
the clearing of the error and DECtape flags, respective- 
ly. Loading status register A from AC through 9 es- 
tablishes the transport unit select, motion control, and 
function, and enables or disables the DECtape control 
riug to request a program interrupt as described in DTRA. 
The accumulator is cleared. 

The contents of both the error and DECtape flags are 
sampled. If any flag is set, the contents of the program 
counter are incremented by one to skip the next sequen- 
tial instruction. 

The contents of status register B are loaded into the 
accumulator by an inclusive OR transfer. The bit 
assignments are as follows. 

ACO = Error flag (EF) 

ACl = Mark track error (MK TRK) 

AC2 = End-of-tape error (END) 

ACS = Select error (SE) 

AC4 = Parity error (PE) 

AC5 = Timing error (TIM) 

AC6-8 = Memory field (MP) 

AC9-10 = Not used 

AC 11 = DECtape flag (DTP) 

The memory field portion of the status B register is loaded 
from accumulator bits 6-8. The accumulator is cleared, 
and the error flags are left undisturbed. 



2.5 FUNCTIONS AND FLAGS OF THE CONTROL SECTION 

Although the instruction set of the DECtape system is simple, the effects of these instructions are not. In this 
section, each of the functions that the TC08 will perform and the possible results of the operation are described 
in detail . 



2.5. 1 Functions of the Status A Register 



2-11 



2.5.1 .1 Transport Unit Select - Each unit con be dialed Into a particular selection address by means of a 
switch on the front of the transport. When the octal code matches the selection address, only that transport 
responds to the TC08 controller. 

2.5. 1 .2 The Motions - GO asserted by loading a 1 into bit 4 allows the selected transport to move either for- 
ward (clockwise) or reverse, according to the contents of bit 3. If STOP Is selected, then the machine does not 
move in any direction, or ceases to rotate In the direction It Is moving. It should be noted that each transport 
remembers the motion it Is selected to perform, and If the TC08 controller selects another transport without stop- 
ping the first, then the transport's memory keeps It moving. The functions are not performed when this transport- 
is not selected, however. 

2.5.1 .3 The Modes - Associated with each of the functions are two modes, called normal and continuous. 
The difference in response for each mode varies with the functions, as explained in the following paragraphs. 

2.5.1.4 The Functions - 

a. Move - The move function Is used to rewind tape. Code 000 of bits 6, 7, and 8 initiates tape 
motion in the selected direction, provided GO is also on. The mark track is read, but only the end of 
tape instruction is decoded. End of tape posts an error flag and causes an Interrupt to the PDP-8. If 
the tape control is unselected but not stopped, it continues to run; however, the end of tape Is not 
detected. The state of mode is Irrelevant. 

b. Search - The search function Is used to search for blocks. When a block number Is detected by the 
mark track, the three-cycle data break control transfers the number Into the address specified by the 
current address register. The current address register is not incremented, so that successive block 
numbers always go to the same address. The word count register Is Incremented, however, as each block 
number is passed. If the mode is set to normal, the DECtape flag is set each time a block number Is de- 
tected. This causes an interrupt, and the program can identify the block number. In continuous mode, 
no interrupt occurs until the word count register overflows. This search operation Is most efficient when 
both modes are used In the following way: 

(1) The current block number Is detected In normal mode. 

(2) The difference between It and the desired block number Is computed, and the direction cor- 
rected, if necessary. 

(3) The two's complement of the difference is loaded into the word count register. 

(4) The TC08 Is changed to continuous mode. 

(5) On the next Interrupt, the transport is over the desired block. The block number is in the 
address specified by the current address register. 



2.5.1 .5 Read Data - This function reads data In either direction and transfers blocks of data Into core memory, 
with the transfer controlled by tape format. In the normal mode, DTF Is set at the end of each block, causing a 
program Interrupt. In the continuous mode, transfer stops and the DTF Is set when the word count overflows; however, 
the remainder of the block in which the overflow occurred Is read for parity checking, after which the DTF is set. 

2-12 



2.5. 1 .6 Read AH - This function allows the reading of oli data bits on tape after the tape motion attains speed, 
The three information tracks are continuously read and transferred to the computer. The mark track is used only 
to check for mark track and end of tape errors. During the normal mode, the DECtape flag is set at each data 
transfer. During continuous mode, the DECtape flag is set only when a word count overflow occurs. 

2.5.1 .7 Write Data - This function is used to write blocks of data in either direction, with the transfer con- 
trolled by the standard tape format. When a word count overflow occurs during the writing of a block of data, 
zeros are written in all the remaining lines of tape until the end of a block; the checksum over the entire 
block Is then written. The DTF is set In a manner similar to that for the Read Data function. 

2.5. 1 .8 Write All - This function allows the writing of all bits on tape even though the Information Is not in 
the standard tape format. The mark track is used only to check for mark track and end of tape errors. The DTF 
is set for the same conditions described for Read All . This mode Is used to write block num.bers on ta^^e* 

2.5.1 .9 Write Timing and Mark Tracks - When the controller Is put Into this mode, it Is ready to format a 
DECtape reel by adding the timing marks and the mark track. In norma! mode, the DECtape flag Is posted 
after each word is transferred to the mark track (every four lines); In continuous mode It Is posted as soon as the 
word count overflows. A complete description of the program is given in the TOG-8 DECtape formatter 
description, available from the DEC program library. 

2.5.1.10 - Enable to Interrupt - The TC08 control has an Enable-to-Interrupt (ENI) function which permits the 
program to remove the TC08 from the program interrupt of the PDP-8 processor. This bit activates It. 

2.5.2 Errors and Flags of the Status B Register 

This register contains 6 bits of error status Information, 3 memory field bits, and the DECtape flag bit. Their 
functions are explained in the following paragraphs. 

2.5.2.1 Error Flag - Bit - This flag is set If any one of the five following error flags come up. These con- 
ditions stop transport motion, except for the parity error (bit 4), and all of them cause a program Interrupt if 
the facility is enabled. 

2.5.2.2 Mark Track Error - Bit 1 - The output from the mark track Instruction register is tested every time an 
Instruction should appear. If one does not, this Indicates that the mark track Is not recorded properly, and that 
an error has occurred. Bit 1 and, therefore, bit are posted. 



2-13 



2.5.2.3 End of Tape Error - If the Instruction register of the mark track decodes an end zone indicator, then 
bit 2 is set and, therefore, bit 0. A subsequent program interrupt stimulates the computer to find out what 
happened . 

2.5.2.4 Select Error - This flag examines and compares various switches and status A functions, and will detect 
four incongruous combinations. These are: 

a. When the transport unit select code loaded into the status A register specifies either more than one 
transport or none at all . This occurs when two selected transports are set to the same number, or none 
is set to the correct code . 

b. When a write function is specified while the WRITE ENABLE/WRITE LOCK switch on the selected 
transport is set to the WRITE LOCK position, which inhibits writing. 

c. When bits 111 are set into the function bits 6, 7, and 8 of status A, indicating a nonexistent 
function. 

d. When the WRTM/NORMAL switch and the function selected do not coincide (e.g., trying to 
format on NORMAL). 

2.5.2.5 Parity Error - This error occurs if the longitudinal parity buffer shows an error at the end of a block 
during a read data function. In normal mode, the error flag is set when the DECtape flag is set. 

2.5.2.6 Timing Error - This flag monitors possible timing errors, which are: 

a . If the data break request is not answered in 30 [js, some of the data is lost. 

b. If the DECtape flag is not cleared by the program before the control attempts to set it again, the 
condition which set it was not serviced, and was probably lost. 

c. If the read data or write data function is loaded into the status A register while the read heads are 
over a data section of the block, the complete block can not be transferred, and an error condition is 
present . 

2.5.2.7 The Memory Field - This three-bit register is set by the computer to specify the memory field to or 
from which the data will be transferred via the memory extension control . 

2.5.2.8 DECtape Flag - This flag, which is constantly referred to in the function descriptions, is set after 
specified operations are completed. It can be cleared by setting a zero into status A bit 11, and will cause an 
interrupt if that facility is enabled by status A bit 9. 

2.6 PROGRAMMING DECTAPE 

In this section, a number of simple programming examples are given to illustrate the principles outlined earlier. 
The PDP-8 programming library makes available many subroutines which are easily incorporated into a user pro- 
gram, so that the user rarely needs to develop his own DECtape handler. 

In each example, it is assumed that there are no other programs in memory, and that the DECtape being used has 
been formatted. The examples are written In PDP-8 Assembler language. 

2-14 



z,6-\ txample !: Rewind lape 

Assume that a DECtape transport number 5 has run into the forward end zone and must be rewound to the reverse 
end zone. A subroutine to do it looks like this: 



Tag 


Instruction 


Remarks 


RWND, 









CLA 


/Clear the accumulator 




TAD (5604 


/Get the status A code 




ION 


Aurn on interrupt 




DTCA 


/clear status A register 




DTXA 

ION 

JMP I RWND 


/Load status A with 560 
Aurn on the PI facility 
/Go back to main progr 





1 

FLAG, 



DECTPE, 



JMP FLAG 

DTSF 
JMP. +2 
JMS DECTPE 
HLT 





CLA 

DTRB 

AND (1000 

SNA 

HLT 

CLA 

TAD (0600 

DTXA 



JMP I RWND 



'This is the interru^^t 
/service routine. 

/This is the skip chain 
/where the DECtape flag 
/is discovered . The 

/program halts if the DECtape flag is not 
/set. When the program was started, 
/it was assumed that no other device 
/was on. The halt indicates an erroneous 
/interrupt by a truant device. 

/Clear accumulator 

/Read status B 

/Mask out all but the end of tape error 

/skip if a bit is in the AC 

/See following note 

/clear the accumulator 

/Get the new status A function 

/Exclusive OR it onto the 

/status A register. This 

/will simply clear all flags, 

/stop the DECtape and set its motion to forward, 

/Go back to the mainsubroutine. 



2-15 



NOTE 

During a move function, only on end of tope error 
can arise. If an inf-errupt occurs and no such error 
is posted, a malfunction is indicated, and the pro- 
gram is halted . 



2.6.2 Example 2: Find a Block 

If transport number 3 is stopped near the forward end zone and must be moved to block number 5 (the current 
address register is CA and the word count register WC), the procedure is to put the controller into search mode 
normal, find out where the unit is, subtract five from that block number, set the two's complement of the result 
into the WC register, and place the controller into search continuous mode. The next interrupt should occur 
when the tape reaches block number 5. The subroutine is called SRCH. 



Tag 


Instruction 



Remarks 


SRCH, 






ION 


/Turn on the PI 




CLA 






TAD (3614 


/Status A code for search, etc. 




DTCA 


/Clear status A 




DTXA 


/Load status A 




J MP I SRCH 


/Return to subroutine 



0. 



0000 



FLAG, 



TAPE, 



J MP FLAG 




DTSF 


/Thh is the same skip 


JMP. +2 


/chain coding as in the 


JMS TAPE 


/previous example. 


HLT 




CLA 




DTRB 


/Read status B 


DCA TEMP 


/Store it away 


AND (0001 


/Mask for DECtape flag 


SZA 


/Flag is on 


HLT 


/No flag - something is wrong 


CLA 




TAD TEMP 


/Return status B 



2-16 






BLKNO, 



Instrucf-lon 


AND (1000 


SZA 


JMP ERROR 


JMP BLKNO 


CLA 


TAD I CA 


TAD (y/ys 


SNA 


JMS WRT 


CLA 


TAD (5 


CIA 


TAD I CA 


CIA 


DCAWC 


CLA 


TAD (0100 


DTXA 


ION 


JMP I SRCH 



Remarks 



/Test for the error flag 

/Go to error subroutine 

/Go to subroutine to get block number 



/Get block number 

/Test for block 5 

/Skip if not zero 

/This is block 5 - start writing 

/Not block 5 

/Get a 5 

N^^i ^ .f^ -. ^ 

/Add present block number 

/2's complement it 

/Pui result in WC 

/clear accumulator 

/Get next status A setting 

/Exclusive OR into status register (continuous mode) 

/Turn on PI 

/Go back to main program. 



2.6.3 Summary of TC08 Timing Data (All times are ±30%) 
Operation 



Time to Answer Break Request 

Data Break Transfer Rate 

Word Transfer Rate 

Block Transfer Rate 

Start Time 

Stop Time 

Turn Around Time 

Time to Change from Search to a Read or Write 
Function 



Time 



Up to 33 |js (± 30%) 

4 = 5 \£ (3 cycles) per word 

One 12-bit word every 133 \ss (± 30%) 

One 129 -word block every 25 ms (± 30%) 

375 ms (± 20%) 

375 ms (± 20%) 

375 ms (± 20%) 

400 ps 



2-17 



2 .7 TC08 OPERATOR CONTROLS AND INDICATORS 

The single switch, WRTM/NORMAL, and an array of lights ore all that the operator of the TC08 controller need 
concern himself with. The operation of the transports is explained in their respective manuals. The TC08 
switch, located on the left-hand side of the logic panel, puts the controller in write timing and mark track mode 
or else in normal, or every other mode, depending on the settings, SWTM or NORMAL respectively. Table 2-4 
summarizes the function of each indicator. Figure 2-7 is a photograph of the indicator panel . 




Figure 2-7 The Indicator Panel 



Table 2-4 
The TC08 Indicator Panel 



Indicator Name 


Indicator Function 


USR 


The Unit Select Register specifies which transport is to be activated, according to the 
following table. 


Bit State 


1 2 


Transport Selected 



1 
2 
3 
4 
5 
6 
7 



I 
1 

1 I 

1 
1 1 
1 1 
1 1 I 


8 or 

1 

2 

3 

4 

5 

6 

7 


MR 


The Motion Register specifies the three possible movements of the reel . These are: 


Bit State 




Function 



1 
2 
3 


o — o — 
o o — — 


STOP 

GO REVERSE 

STOP 

GO FORWARD 



2-18 



Table 2-4 (Cont) 

■ no i\^\J\j iiiCii <^ui v^i ruiici 



Indicator Name 


Indicator Function 


FR 


This four-bit Function Register specifies one of seven possible operations in either of 




two modes. BIT on a - normal mode. 




BIT on a 1 - 


continuous mode. 


Bit State 


1 2 3 


Function 
MOVE 










1 


1 


SEARCH 




2 


1 


READ DATA 




3 


1 1 


READ ALL 




4 


1 


WRITE DATA 




5 


1 1 


WRITE ALL 




6 


1 1 


WRITE TIMING AND MARK 


ENI 


7 


1 1 1 


UNUSED (Causes select error) 


Enable the interrupt when o 


n Indicates that the TC08 can cause a program interrupt 




when an error flag or the DECtape flag is set. 


EF 


Thi? f!nn i« C^f if rtn\f nno nf ¥na f'\/a fnWfwAi'nn armr f\rtnc i^nma itr\ TUacia /»/-it-i/^ itJ^iic 




stop transport motion, except for the parity error of bit A, and all cause a program 




interrupt if the facility is enabled. 


MK 


The output from the mark track Instruction register Is tested every time an Instruction 




appears. If no Instruction appears, this Indicates that the mark track is not recorded 




properly and therefore an error has occurred. MK and therefore EF are set. 


END 


If the instruction register of the mark track decodes an end zone Indicator, this flag 




and EF are set. A subsequent program Interrupt stimulates the computer to find out 




what happened . 


cr 


This flag examines and compares various switches and status A functions, and will 




detect 4 incongruous combinations. These are: 




a. When the transport unit select code loaded Into the status A register 




either specifies more than one transport or none at all . This occurs when 




two selected transports are set to the same number, or none Is set to the 




correct code. 




b. When a write function Is specified while the WRITE ENABLE/WRITE LOCK 




switch on the selected transport Is set to the WRITE LOCK position, which In- 




hibits writing. 




c. When bits 111 are set into the function bits 6, 7, and 8 of status A, In- 




dicating a nonexistent function. 




d . When the switch WRTM/NORMAL and the function register do not co- 




incide (I.e. , trying to format on NORMAL). j 



2-19 



Table 2-4 (Cont) 
The TC08 Indicator Panel 



Indicator Name 



Indicator Function 



PAR 



TIM 



MF 

DTF 

DF 

W 

WC 
UTS 

STATE 

BM 

RC 
D 

F 
CK 

MC 

DTB 

WB 



This error occurs if the longitudinal parity buffer shows an error at the end of a block 
during a read data runctlon. In norma i mode, tne error fiog is set wnen tne DECtape 
flag is set. In continuous mode the error is set after the word count overflows for the 
block it overflows in. The parity error flag cannot be set after the DECtape flag has 
has been set . 

This flag monitors possible timing errors, which are: 

a . If the data break request is not answered in 20 ps, some of the data 
is lost. 

b. If the DECtape flag is not cleared by the program before the control 
attempts to set it again, the condition which set it was not serviced, and was 
probably lost. 

c. If the read data or write data function is loaded into the status A register 
while the read heads are over a data section of the block, the complete block 
cannot be transferred, and an error condition is present. 

These three lights show the contents of the memory field register. 

This light reflects the state of the DECtape flag. 

The Data Flag is set when the TC08 controller needs to transfer a data word through 
the three-cycle break. 

This flag, when set, indicates that a write all function is occurring. 

The Word Count flag is set whenever the word count register overflows. 

This Up-to-Speed flip-flop is set as soon as the tape transport reaches an acceptable 
speed . 

These bits make up the TC08 state generator, a switched-tail ring counter, which 
steps from an idle state through five other states and back to idle as a block passes 
the tape heads. 

Block Mark is the first bit to which the state generator moves. It is set when forward 
block mark is in the data buffer. 

The Reverse Checksum state occurs when the Reverse PCC Mark cell is encountered. 

The Data state starts with the first block that contains data (the Reverse Final Mark) 
and finishes when the next-to-last data block (the Prefinal Mark) passes the read 
heads . 

The Final state occurs during the last cell which contains data (the Final Mark). 

The Checksum State occurs when the PCC Mark cell passes the heads. During this 
state, the checksum is deposited in the PCC Mark, if the TC08 is writing; it checks 
for a parity error, if the TC08 is in a read operation. 

These three bits represent a three-bit switched-tail counter composed of bits MCOO, 
MCOl, MC02. 

The Data Buffer holds 12 bits of data on its way to or from the computer. 

The Write Buffer receives data from the data buffer. It feeds the transport during a 
write operation . 



2-20 



Table 2-4 ''Cont'^ 
The TC08 indicator Pane! 



Indicator Name 



Indicator Function 



LPB 

CO, CI, MKT 
WINDOW 

WTM 



The Longitudinal Parity Buffer calculates a checksum of data that is read from or 
written to the magnetic tape. 

These are the flip-flops which constitute the counters of the timing generator. 

The Window Register is a simple shift register which receives the instruction codes from 
the mark track and uses the codes to set the State Generator. 

This means the SWTM/NORMAL switch is in write timing and mark track mode (SWTM), 



2-21 



CHAPTER 3 
TC08 - TC08N LOGICAL OPERATION 

In Chapter 3, the logical operation of the TC08 gnd TC08N controllers is explained. Because the difference 
between the two controllers is simply a matter of level converters, that is, the two are logically Identical, 
the term TC08 will be used for both unless otherwise indicated. 

3.1 A REVIEW OF MAGNETIC TAPE RECORDING 

DECtape uses a recording technique variously known as double pulse, phase modulation, or "Ferranti logic". 
Because the design of the TC08 reflects this recording technique, these recording methods are reviewed in this 
section . 

3.1.1 Magnetic Recording In General 

Three basic elements are required to make and reproduce a magnetic recording: 

a. A device which responds to an electrical signal by creating a magnetic pattern in a magnetizable 
medium . 

b A mririi-igf Irakis rrK^rliiim \A/hi(~l-i \A/i I I i~nnfnfm tn nnri noirl trifa mnnn*afir nnttprn . 
K^ . ,y 1,,^^. .^. .~»».x .,,ww,.N^.., ,,.,.^ _„...^ ^ _.._ . J, ._ I _.... 

c. A device which can detect the magnetic pattern and convert it back to the original electrical 
signal . 

These three elements take the physical form of the record head, the magnetic tape, and the reproduce head, 
respectively. The addition of electronic amplification and a mechanical tape handler, produces a basic 
magnetic recorder. Note that the record and reproduce heads are often combined Into a single read/write head, 

3.1.1.1 The Physics of Recording and Reproducing - A record head Is similar to a transformer with a single 
winding In that signal current flows in the winding, producing a magnetic flux In the core material . The core 
of the record head is built In the form of a closed ring; but, unlike a transformer core, the ring has a short non- 
magnetic gap in It. When this gap Is bridged by magnetic tape, the flux detours around the gap through the 
tape, completing the magnetic path. The magnetic tape is a ribbon of plastic on which particles of magnetic 
material have been uniformly deposited. As the tape moves across the record head gap, the magnetic material. 



3-1 



or oxide, is subjected to a flux pattern proportional to the signal current in the head winding. When the tape 
leaves the head gap, each tiny particle retains the state of magnetization that was last imposed on it by the 
protruding flux. Thus, the actual recording takes place at the trailing edge of the record head gap. A simpli- 
fied diagram of the recording process is shown in Figure 3-1 . 



To reproduce or recover the original signal, the mag- 
netic pattern on the tape is moved across a reproduce 
head. Here again the nonmagnetic gap of the head is 
bridged by the magnetic oxide of the tape. Lines of 
flux are shunted through the core, proportional to the 
magnetic gradient of the pattern on the tape which is 
spanned by the gap. The induced voltage in the head 
winding follows the law of electromagnetic induction: 
e = N d$/dt. It is important to note that the repro- 
duced voltage is not proportional to the magnitude of 
the flux, but to its rate of change. 



Suppose the signal to be recorded on a tape is a sine- Figure 3-1 Simplified Diagram of the 

,, , -L -1 L A • /o rr\ XI 1. • Magnetic Recording Process 

wave voltage described by A sin (2tt ft). The current in ^ 

the record head winding and the flux 4> through the 
record head core will be proportional to this voltage. 

When the tape retains this flux pattern and regenerates it In the reproduce head core, the voltage in the re- 
produce head winding will be 




NONMAGNETIC 
GAP 



PLASTIC 
BASE 



TRAILING 
EDGE OF 
GAP 



where 



re pro 
d* d 



dt 



d$ 

" IT 

. A sin (2 tr ft) 
dt 

2 TT fA COS (2 IT ft) 



The reproduce head acts as a differentiator so that the reproduced signal is actually the derivative of the re- 
corded signal, and not the signal itself. This point is important, and is referred to later in the text when the 
principles of DECtape formatting are discussed. 

3.1.2 The DECtape Read/Write Electronics 

The TU55 and TU56 tape drives have 10 heads, each of which can record and reproduce. These heads are 
divided functionally into five pairs; one pair to record and reproduce the timing tracks, one pair for the mark 
tracks, and three pairs to record and reproduce the data tracks. 



3-2 



pji-inrg 3~2 shows th6 sisctronics of o t^'^ica! "^Qir conslstirr^ of two read'writs heads wirsd in seriss center 
rapped to ground, a G888 writer, and a G888 reader. The writer is simiiar to a push/puii amplifier; it can 
drive current in either direction, depending on the relative polarity of its inputs. It can drive an almost square 
current pulse into the heads. The reader is a high-gain amplifier with positive feedback which will respond to 
a 500 pV input. It is provided with a test point which samples the output voltage of its first stage. That stage 
is simply a linear amplifier with a gain of 100. Subsequent stages consist of a zero crossing detector and a 
limiter which then drives a 7400 series TTL gate. The module is discussed in greater detail in Chapter 6. 

The G888 receiver oscillates if it sees no input voltage greater than 500 pV. This characteristic is utilized by 
the up-to-speed logic of the timing generator (see Paragraph 3.2.1 .2). 

3.1.3 The DECtape Recording Technique 

Suppose that a binary number 1001 10 is to be written on one track of the magnetic tape surface, using the 
electronics of Figure 3-2. Waveform A shows the current pulses in the head windings when ordinary recording 
is used. Since the maximum rate of current change is between Is and Os, during these changes the maximum 
flux is induced into the magnetic surface and the subsequent passage of a read head develops a maximum output 
voiTQge \d). /^. long brnng or vjb or is renQs to iook hks one long u or one long i . 

It is possible to decipher such signals, but it is much more desirable to provide a writing technique that causes 
some positive action in the center of each bit time. This is accomplished by changing the phase of the writing 
current pulse in the middle of a bit time. The method is called phase modulation. 

To produce phase modulation, the normal steady state logic to be stored must be changed before it reaches the 
write head. This is done by using a special write buffer (Figure 3-2). The write buffer is loaded with the bit to 
be written during the main timing pulse, and then complemented at a half clock pulse. (In the TC08 these are 
called TPOO and TPOl, respectively.) The half clock occurs at the same frequency as the main clock, but it is 
displaced by 180 degrees. The effect is to place a wave of flux on the tape as it passes beneath the head. The 
polarity of this wave depends on the bit which is loaded during the main clock pulse, which, in turn, depends 
on whether it was a or a 1 . 

The read voltage is amplified and clipped in the reader. It is then gated with the half-clock pulse into the data 
flip-flop, yielding the written version delayed by half a clock time. 

Notice that the voltage readout peaks near the center of each bit time, whether a string of Os or Is occurs or 
not. The choice of polarities is arbitrary, but there is a distinct 180-degree difference between a and a 1 
readout . 



3-3 



READ/WRITE ELECTRONICS 




-TPOO 

-DATA IN (HIGH ON A1) 



MAGNETIC TAPE 



READ/WRITE SIGNAL 



WRITE 
BUFFER 



(WRITE CURRENT) 



(WRITE VOLTAGE) 



X 

FLUX 



READ VOLTAGE 
_dx 
" dt 



OUTPUT 

OF READER 

V„ 



2.5V 



+ 150 ma 




lt 



TU 



NOTE THE 90» PHASE SHIFT 




Vr IS CLOSE TO A SINE WAVE BECAUSE OF 
HEAD CHARACTERISTICS 



Figure 3-2 DECtape Read/vVrite Electronics and Waveforms 



3-4 



3.2 THE DECTAPE SYSTEM 

In this section, the TC08 controller is divided into subunits, and each subunit Is analyzed. The subunits are 
so interrelated,- however, that it is impossible to present them in any order of appearance which will not 
require the text to reference sections not yet mentioned. The reader is urged, therefore, to read the chapter 
several times, and keep in mind the overall block diagram. 

The DECtape system comprises a controller, the TC08, and up to 8 TU55 or 4 TU56 transports. Each transport- 
contains a tape deck with reels, reel motors, tape guides, and 10 read/write heads. It also includes a rotary 
selection switch and several functional switches. For complete descriptions of the transports, refer to their 
respective manuals. 

The logic circuits of the transport command tape movement in either direction over the heads. These circuits 
can be controlled by the TC08 under the direction of its status register. 

3.2.1 The DECtape Controller 

A block diagram of the DECtape TC08 controller is shown in Figure 3-3. It consists of a 12-bit command 
register, a 6-bit status register, a 12-bit data register, a 6-bit parity register, a 6-bit state generator, a 9-bit 
window register, a timing generator, and the l/O logic. The command register selects the mode of operation 
(read or write), the transport which is to operate (transport 6), and the direction of tape motion. The data 
register buffers the information between the computer and the transport, while the parity register holds the 
checksum. The window register decodes the mark track and sets the state generator into the correct modes (data, 
parity, block number) according to the position of the tape over the heads. 

The timing generator writes the timing track during write timing and mark and reads it back during ordinary 
operation. It contains a set of counters which overflow after every 4 lines, or a 12-bit word, and after every 
6 lines, or a complete mark track cell . These counters, together with the timing pulse, regulate all the other 
blocks. 

The status register records any timing or parity errors which occur during operation. The l/O logic posts a data 
flag (DF) when the controller wants to transfer data through the 3-cycle break to or from memory, and the 
DECtape flag (DTF) whenever an operation has been completed. 

3.2.1 .1 The Command Register - A simplified diagram of the command register and the tape drive it controls 
is shown in Figure 3-4. It is divided into 4 sections: the unit select register, whose code must match the unit 
select switch code of the transport; the motion register, which sets the motion and direction flip-flops of the 



3-5 



TIMING TRACK- 



TIMING GENERATOR 



TIMING PULSES 



MARK TRACK- 



TIMING PULSES AND COUNTERS 



SYNCHRONIZING PULSE 



#.98765432 1 



WINDOW REGISTER LOGIC 



1 2 3 4 5 



STATE GENERATOR LOGIC 



DATA TRACK 1 



DATA TRACK 2 



DATA TRACK 3 



n 



n 



10 7 4 1 — *■ 1 



n 



DATA REGISTER 
a WRITE BUFFER LOGIC 



TO TRANSPORT- 
SELECT LINES 
AND COMMAND 
REGISTERS OF 
TRANSPORT 



3 



a 



O" 



5 2 



LONGITUDINAL 
PARITY BUFFER 



DECTAPE 
FLAG 

D 



I/O CONTROL 
LOGIC 



D 

DATA 
FLAG 



c=c> 



TO THREE 
CYCLE DATA 
BREAK POP -8 



( STATUS A LOGIC ) 



I/O BUS 
TO POP-8 



lOT 

DECODERS 
AND LEVEL 
CONVERTERS 



I/O BUS IN 



01 23456789 10 11 



COMMAND REGISTER 



01 2345678 



STATUS REGISTER 
(STATUS B LOGIC) 



I/O BUS OUT 



Figure 3-3 The TC08 DECtape Controller Block Diagrar 



3-6 



I/O BMB03(1)H- 
I/O BMB04{1)H- 
I/O BMB05(1 )H- 

1/0 BMB 06(1 )H- 
I/O BMB 07(1 )H- 
1/0 BMB 08(I)H ■ 



CSTA L 
PWR CLR L 



1 UNIT 



SELECT REGISTER 



n 



I/O BAG 00(1)H- 



~AlH> 



I/O BAG 01(1)H- 



■\ 



^^•N^— RSTA H 
y l-"^—- RSTA L 



I/O BAG 020 )H • 



^'X;;— -CSTA H 



J 



N.f. B-XSTA 

^ — I /UO — XSTA L 



PWR GLR L- 




1/0 BAG 03(1)H- 



t_M> 



I/O BAG 04(1)H 



B-RUN(0)L 
PC + ES L 



\^ M-STOPL 



I/O BAG 05(1)H- 



I/O BAG 06(1 )H 



I/O BAG 07(1)H 



t>r= 



\y^ 



-Ty^ 



FUNCTION 
REGISTER 



A. J 



tCH> 



I/O BAG 08(1)H- 



I/O BAC 09(nH- 



L_ 



J 1 

USROO 



ENABLE 



L-|k 



J 1 

USR01 
K 



USR02 
K 



I Jo TO STA lI 

MOTION 
REGISTER 



J 1 

MROO 
K 

3: 



J 1 

MRO! 
K 



^=1 



J I 

FROO 
K 



J 1 

FR01 
K 

IT" 



J I 

FR02 
K 

IT" 



J 1 

FR03 



-'>^r^A 



J 1 

ENI 
I — IK 



'INTERRUPT REGISTER 

I I 



BINARY 
TO OCTAL 
CONVERTER 



M16t 



^^^Ty™!^ 



^^^eaTVl^^^ 



♦— c 
c 



t-c 



D 1 

BMROO 
G 

IT" 



a\_ T REV L 
M633 Jo -= 



KI 



D 1P 

BMR01 
L_|G 



M16 



2l 






"~^^^63ry™5_k. 



M633 jO- 



, V ^ T01 L 
3 10 — — 

V» TOO L 

3 b — ^^ — 



vny — 



M\_ T PWR CLR L 
M633 JO — 



aV, T STOP L 
M633 b — 



' j^r\ "^°^ 



- SEH 
— SE L 

- WRTM H 

- WRTML 

- WRITE ALL H 

- WRITE ALL L 

- WRITE DATA H 
— WRITE DATA L 

- READ ALL H 

- READ ALL L 

- READ DATA H 

- READ DATA L 

- SEARCH H 

- SEARCH L 

- MOVE H 

- MOVE L 



BINARY 
TO OCTAL 
CONVERTER 



DECTAPE 
TRANSPORT 



°4 
J>3 



UNIT SELECTOR SWITCH 



X>^>-f 



REVERSE FORWARD STOP GO 





1 

MOTION 
D 



h 



Figure 3-4 Command Register 



3-7 



selected transport; the function register, which is decoded to determine in which of the seven modes the 
controller will operate; and, finally, the enable flip-flop, which, when set, allows the controller to post a 
program interrupt request to the computer. The motion register is double buffered so that its effects will not 
be felt until the unit select register has established itself on each transport. Without this delay, two transports 
could pick up the same motion command. 

Each of the flip-flops in this register is a JK which will complement whenever its appropriate input line is 
asserted and the XSTA pulse issued through the lOT instruction. The buffered motion registers are D-type 
flip-flops which are jammed with the delayed XSAD pulse, XSA DY H. 

Device code 76 with lOP 2 complements selected flip-flops, and code 76 with lOP 4 (CSTA) clears all . 
Figure 3-5 shows the timing for the various versions of the PDP-8. 

Flip-flops MROl and BMROl , which select the stop or go function, clear and stop the transport if a CSTA is 
issued, if power clear is issued, if the computer stops (B - RUN(O) L appears), or if any error except a parity 
error occurs (PC + ESL). 

3.2.1 .2 The Timing Generator - This part of the controller (shown simplified in Figure 3-6) has 4 subsections; 
the timing track write logic, the up-to-speed logic, the timing track read logic, and the counters. 

The timing track write logic is used only when a tape is being formatted. Its M401 clock is enabled when the 
switch is on SWTM and this mode is selected. This 120-kc clock starts a two-bit switched tail counter CKOO, 
CKOl . CKOO is used to write the timing track, and CKOl , 90 degrees out of phase, generates the internal sig- 
nals to the controller for writing the mark track. The reason for this arrangement is worth further explanation. 
The timing signals that are being recorded now will later be read back and used to read and write data. We know 
irom previous tueory tnot tnese timing tracKS wmi read uOck 9v/ i^egrees out of phase from Vy'hen they were written. 
So that the mark track being written -corresponds in phase to the data to be written later, the mark track must be 
written 90 degrees out of phase with the presently generated timing track. This is accomplished by using CKOO 
to write the timing track, but CKOl, which is 90 degrees out of phase, to write the mark track. 

The up-to-speed logic prevents timing pulses from entering the main controller until the tape motion has reached 
an acceptable speed. It does this by monitoring the frequency of the timing pulses coming off the tape with two 
delays. As noted in Paragraph 3.1 .2, the G888 reader oscillates if it detects no input signal above 500 pV. 
The first delay, which is fired whenever the computer requests a change of transport or motion, allows the tape 
to reach a speed at which the G888 stops oscillating and starts responding to the timing track (120 ms). The 
next delay, an integrating-one-shot, fires only after the timing track signals reach a specified frequency and 
the first delay has timed out. This sets the up-to-speed (UTS) flip-flop. Gates (3) are enabled, and timing 
pulses TPOO and TPOl are passed on to the rest of the generator. 



3-8 



SIGNAL 
NUMBER 



START OF iOT 
FETCH CYCLE 



START OF FETCH 

CYCLE FOR NEXT 

INSTRUCTION 



SIGNAL 
NAME 



I/O BMB 



lOP 1 H 
lOP 2H 



I0P4H 



-750 -950 NS 



-^ 



J\. 



INSTRUCTION IN BMB 



1.3-1.6/iS- 



500- 
600 NS 



CLEAR STATUS A 



2-2.5/iS- 



500- 
600NS 



XOR AC TO STATUS A | 



^^ 



2.7-3.4/iS- 



TIME 



i^s 



1 r 

2/iS 3/iS 

IOT INSTRUCTION 4.25 /iS 



-► 500- 
600 NS 



t^S I 



NOTE: 

THE I/O BAC 00-11 LINES ARE CONTINUALLY REFLECTING 
THE CONTENTS OF THE ACCUMULATOR. 



Figure 3-5A Command Register Timing with PDP-8/L 



SIGNAL 
NUMBER 



START OF IOT 
FETCH CYCLE 



START OF FETCH 

CYCLE FOR NEXT 

INSTRUCTION 



SIGNAL 
NAME 



I/O BMB 
03(1)H-08(1)H 

! P 1 H 

I0P2H 

I0P4H 



1 



INSTRUCTION IN MB- 



CLEAR STATUS A 



■2.25^5- 



400 NS 



XOR AC 
TO STATUS 

— ^^17= 



-3.25^S- 



400NS 



TIME 1/i.S 2^S 3/iS 

• IOT INSTRUCTION 3.75^S 

NOTE: 

THE I/O BUS 00-11 LINES ARE CONTINUALLY REFLECTING 

THE CONTENTS OF THE ACCUMULATOR. 



3.75/iS 



SIGNAL 
NUMBER 



Figure 3-i»B Command Register liming with KUP-8 



SIGNAL 
NAME 



START OF IOT 
FETCH CYCLE 

I 

I 



START OF FETCH 

CYCLE FOR NEXT 

INSTRUCTION 

I 

I 



I/O BMB 
03{1)H-08(1)H 

I0P1 H 

I0P2H 

I0P4H 



-750 NS- 



3E 



-INSTRUCTION IN BMB- 



.5/iS- 



700 NS 



2.5/iS- 



€ 



CLEAR STATUS A 



» 700 NS 



XOR AC 

TO STATUS A 



-3.5/iS- 



TIME 



IMS 2/i.S 3/iS 
IOT INSTRUCTION 4.25 /iS 



700 NS 
4/iS 



4 



NOTE : 

THE I/O BAC 00-11 LINES ARE CONTINUALLY REFLECTING 
THE CONTENTS OF THE ACCUMULATOR. 



Figure 3-5C Command Register Timing with PDP-8/l 



08-0435 



3-9 



The timing track signal is received by the G888 reader, which then generates two complementary signals TTRK (0)H 
and T TRK (1)H on the leading and lagging edges of the timing pulse. If the controller is not in Write Timing and 
Mark Track Mode, gates (1) are enabled, and these signals each trigger their respective 10 |js delay. These de- 
lays serve two functions: they do not accept any other pulses for their period, thus eliminating any noise which 

may follow the pulse; and they also disable their opposing signal at gate (3), thus eliminating any possible cross- 
4.~it Uc.4,.,^£>« t-Uffl 4....^ cr^^riw ;f ^Ua ^,^k,*.^«ii^^ Ic :« \a/..;».^ t;«,:«« j kA^r-L t^^^l ka^^^ «~i-«o f'}\ - — 1>' — ' 

lUirx kyClvv^oil lilC I WW. liiiuiipr, ii iiio \^williwil^l lo III vyilic lliiilli^ v^ll«^ iTiuirx iius^rx ivivyt^o, ^Ul c?o \^/ 1^1 c Ol lUk^l ^v^ , 

and the counter CKOl generates the proper timing pulses. 

Finally, the timing pulses feed two sets of counters (see Figure 3-7), COO and MKT, which trigger on TPOO and 
are used to keep track of the number of bits that have been read from or written into a track, up to 4 (which 
means a 12-bit word). CO! triggers on TP01 and divides its pulses by 2. The value of this will become obvious 
later. 

The three-bit ring counter, MC00-MC02, recycles every 6 bits per track (thus every cell). It is used to 
synchronize the mark track cells as they are decoded from the window register. 

These counters are synchronized at gate (B) as the window register decodes the interblock sync mark (725 or 525) 
during search, read data, read all, or write all functions. For read all and write all this synchronizing occurs 
on the first block after the up-to-speed flip-flop is set, but not again until it resets. 

During search and read data, the controller resynchronizes after every block. 

3.2.1 .3 The Window Register - This is o 9-bit shift register (see Figure 3-8) which remains cleared until the 
UTS flip-flop has set. It then begins to shift the mark track code in through its least significant bit. No de- 
coding is carried out until WOl, the most significant bit, is set. This bit latches on a one and decoding begins. 
Requiring WOl to latch before decoding guarantees that at least 9 bits have been transferred, and, therefore, 
that the code is a valid one. The decoding shown in Figure 3-8 is carried out for the benefit of the state gener- 
ator. Decoding for other subunits is shown in their respective diagrams. 

3.2. 1 .4 The State Generator - As the window register decodes information from the mark track, the state 
generator responds by interpreting the code appropriately and stepping through six states as different regions of 
a block appear. This process guarantees that a block of data is handled completely; that is, that the controller 
does not start writing half way Into a block because It has detected a data region on the mark track. 

The state generator in Figure 3-8 Is 6 bits long. It starts off in the Idle state and steps from that through a 
start block, a parity check, a data, a final, and a checksum state, as a complete block passes the read heads. 
It cannot leave the Idle state unless It sees the beginning of a block, so there Is no chance that a block will be 
partially written Into or read. 



3-10 



TIMING TRACK WRITE LOGIC 



WRTM H- 

SWTM H- 

U+MDY H- 



'REN (1)H- 



y 



TM EN H 




\> 




M401 CLOCK 
8.5m SEC 



D 1 
CK01 
C 



D 1 
CKOO 
C 




G8S8 



WRITER 



TM EN H 



TIMING TRACK READ LOGIC 



CKOl (0) 



^s®y 



CONNECTOR TO TIMING 
TRACK HEADS. 




M302 
10m SEC 



T TRK(O) H 



T TRK (1) H 



CKOl (1)H 




"- ®\-r^^ 



TPOO L TPOO H 



TP01 L TP01 H 




M602 




J 


[X 




L^ 






1 



TPOO A L TPOO A H 



TP01 A L TPOl A H 



jo— *— 01^ f~B y ^^°^ 0— *— o^>— I 



UP TO SPEED LOGIC 



BACOl (1) L 
BAC01 (1) L 
BAC02 (1) L 
BAC0 3 (1) L 
BAC04 (1) L 



+ 3V 



(lOT TO LOAD STATUS A) 



XSTA 



■ov 



^^C>r^_Z""°'"'^Z> 



4 ^ 



M-STOP L 



120ms 
ONE SHOT 



TO STATE L 



Figure 3-6 Timing Generator 



3-n 



■TPOO H 



D 1 

COO 

C 



TPOOH— *- 
SYNC H 



-TP01 H 



TPOO H- 



(D 



H 






® 



D 1 

MKT 
C 



D 1 

COl 
C 



I 



D 1 
MCOO 
C 



D 1 

MC01 

C 



D 1 
MC02 
C 



J 



W01 (1)L-C[ 
W05(1 ) 



A 

^-L/ 




W03(1)H — 
W04(1 )H- 
W06(0)H- 
W07{1 )H- 
W08(0)H 
W09(1 )H- 



UTS(O) 



SEARCH 
"\ READ DATA 

y 



t|~~> 




725 
525 



SYNC H 



Figure 3-7 The Counters 



3-12 



WOKDL — O 
W05(1)L — C 



CO 

I 



W02(0) H 
W03(1) H 
W04{0) H 
W06(0) H 
W07(1) H 
W08(1) H 
W09(0) H 

WOKD H 
W03(0) H 
W04(0) H 
W05(0) H 
W06(l) H 
W07(0) H 
W08(0) H 
W09(0) H 

W01 (1) H 
W04(1)H 
W05(1)H 
W06{1) H 
W07(0) H 
W08(1)H 
W09(l) H 

MCOO(O) H 

MC02(1) H 

COUI) H 



C00(1)H — 

C01 (0) H — 

MCOOdlH -— 

MCOl (0)H — 

MC02(0)H — 

MKT(0)H — 





THE STATE GENERATOR 



MK BLK MK H 



(526) 



^ 



TO STATE L 
BLK IN SYNCH 




STIDLE(I) H 
rC5y ^\ST BLKMK(I) H 



{<Ji S.STBLKMK(1) 

^ / MK BLK 

" W ^ ^ START H 
MION 



STREVCK(l) H 




> 



DATAd) H 



MK BLK 

END H 



ST FINAL(I) H 



/473' 
f 573 
1673/ STCK(1)H 




ST BLK 
MK 



t— C 



I 



ST REV 
CK 



I 



D 1 
DATA 
rHC 



I 



ST 
FINAL 



I 




>1 



DATAd )L — dl 
STFINALO)L 



D 1 



ST CK 



C 



X 



.00 L -ci j\y^ ^ y ^^w^ 



£. 



D 1 



ST 
IDLE 



C 




RD ENH 



THE WINDOW REGISTER 



+ 3V 



RDMKd) H 

(FROM MARK 
TRACK READ 
HEAD) 



TO W L 

TP01 H 

(SHIFT THE 

WINDOW REGISTER) 



D 1 
WO 9 
C 



I 



2 



D 1 
WO 8 
C 



I 



S 



D 1 
W07 
C 



I 



SI"T2 



D 1 

W06 

He 



I 



D 1 
W05 
C 



I 






D 1 
W04 

-He 



I 






D 1 
W03 

Hc 



I 



D 1 
W02 
I— |C 



I 



Ki 



D 1 
W01 
C 



Y 



^ NOTE THAT W01 LATCHES, GUARANTEEING THAT THE TAPE HAS BEEN MOVING LONG 
ENOUGH TO HAVE SHIFTED 9 PLACES BEFORE A VALID MARK TRACK CODE IS 
ENABLED 



Figure 3-8 The Window Register and State Generator 



Table 3-1 shows the relationship between the window decoding and the mark track, and their functions within 
the controller. Note that the mark track code over any given cell depends on the direction of motion of the 
tape. If the tape is reversed, then the mark track codes are transformed into their obverse complements; i.e., 
73 ■* 10, 51 -*32, 45 ■*26, 70 -*70, and 25 -*25. The result is the same order of codes on the mark track re- 
gardless of the direction of the tape. 

3.2.1 .5 The Data Buffer - Figure 3-9 shows a simplified schematic of 4 bits of the 12-bit data buffer. During 
a read operation, the data buffer shifts the output of the three read heads into three 4-bit shift registers at time 
TPOl . When the buffer fills, the data flag is set (l/O LOGIC) and the buffer is transferred into Memory. 

During a write operation (when Write Enable (WR EN (1)) is asserted), the data buffer is loaded from memory, 
then alternatively shifted into the three-bit write buffer which is complemented on TPOl . The direction of the 
transition during complementation determines whether a 1 or a has been shifted into the word buffer, and 
thus what is written on the data track . 

At the end of a block during a write operation, the LPB (parity register) is jammed into the data buffer and word 
buffer and written into the appropriate cell . During a read operation, the parity register Is tested for possible 
error . 

Timing diagrams for these operations are discussed later. 

3.2.1 .6 The Longitudinal Parity Buffer - This buffer (shown in Figure 3-10) is initiated (zeroed) when the 
ST REV CK(1)H mark passes over the read heads. From here on each data bit complements a parity flip-flop if 
it is a zero. There are two sets of three flip-flops in the LPB. A set samples the incoming data tracks every 
alternate timing pulse. When the end of the block is reached the result of this calculating is either deposited, 
if the machine is writing, or tested for error, if it is reading. 

The error testing is done by regarding the checksum deposited at the end of the block as a data word. After this 
word is seen by the LPB, the LPB should be all ones, as shown in the following: 

Let t define the operation between data bits on any track as performed by the LPB 
Let A and B represent two bits (or two strings of bits), 
i .e., AtB = AB + AB = C = checksum 
Then AtBtC =CtC =CC +CC = 1 

Complete timing diagrams for these operations are discussed later. 

3.2. 1 .7 The l/O Control - All of the data transfers between the computer and the DECtape take place through 
the 3-cycle data break facility. The control logic which handles these transfers consists of a data flag (DF) to 
request the transfer, a word count overflow flag (WC) which is set when the word count overflows, and the data 
buffer which receives and transmits data and miscellaneous gates. Figures 3-11 and 3-12 show a simplified 
schematic of the logic and the associated timing. 

3-14 



lable ,5-f 



Mark 
Track 
Code 


Name 


Window 
Code 


Name 


Function 


55 


REV END 
MARK 


555 


None 


This code requires no operation. It indicates that the 
tape is leaving an end zone. 


25 


INTERBLOCK 


725 


SYNCH H 


This code is used by the timing generator to synchronize 




SYNC 


525 




its counters with the beginning of a block. It occurs 
between blocks and at either end of the tape. 


26 


FORWARD 

BLOCK 

MARK 


526 


MK BLK MK 


This code occurs when the block number is In the data 
register. During a search, the DF Is set and a transfer 
is carried out. This code also steps the state generator 
from IDLE to ST BLK MK. 


32 


REVERSE 


632 


MK DATA 


This Is a no-operation code which gives the computer 




GUARD 




SYNC 


time to respond to the block number It has found in 26. 




MARK 








10 


LOCK 


610 


MK BLK 


This code steps the state generator from ST BLK MK to 




MARK 




START 


ST REV CK (Reverse Checksum). During this state, the 
LPB Is initiated. 


10 


REVERSE 


410 


MK BLK 


The same code also steps the state generator to DATA; 




PCC MARK 




START 


the controller then carries out data transfers. 


10 


REVERSE 


410 


MK BLK 


No action is taken on this code here, except that the 




FINAL 




START 


controller checks to be sure It Is decoded. The first 




MARK 






data block Is happening. 


10 


REVERSE 


410 


MK BLK 


Again no action Is taken. This indicates the second 




PREFINAL 




START 


data block Is happening. 


70 


DATA 
MARK 


470 


MK DATA 


These codes Indicate that a data cell Is under the 
heads . 


73 


PREFINAL 


473 


MK BLK 


This code Indicates that the last data cell Is about to 




MARK 




END 


happen. The state generator switches to ST FINAL. 


73 


FINAL 


773 


MK BLK 


This Indicates that the last data cell has passed the 




MARK 




END 


heads. The state generator switches to ST CK (Check- 
sum) to deal with the parity checksum. Then the state 
generator goes to IDLE. 


73 


PCC 


773 


MK BLK 


The longitudinal parity checksum is stored in the PCC 




MARK 




END 


MARK cell . No operation occurs when MK BLK END 
is decoded . 


73 


REVERSE 
LOCK 

MARK 


773 


MK BLK 
END 


No operation . 


51 


GUARD 
MARK 


751 




No operation. This code becomes 32 when the tape 
is travelling In the opposite direction. In this direction 
it does nothing . 


45 


REVERSE 
BLOCK 

MARK 


545 




No operation . 



3-15 



MKT(0)H- 
TPO t AH- 



WRITE DATA H 

ST FINALd )H — 
MKBLKENDH — 



LPB03(1)H LPB00(1)H 

LPS TO DB 





FROM 
TRANSPORT 
READ HEAD 




RD 00 ( 1) H 



COOd )H 
C01 (1 )H-\ 



COO(0)H 
C01{0)H- 



I 

zr WR EN{1 )H 



TP01 H- 

FROKI )H- 
TPOOHH 

FROKOIH ■ 
TPOt H- 

MC01(0)H- 
WRITE DATAH- 
STREVCK(1)H- 

WC (1 )H 
W-1NH(0)H- 

WRITE ALL H- 

MKT (1 )H- 
FR01 (1)H 



D 1 

DB 09 
C 



D I 

DB 06 
C 



D I 

DB 03 
C 



SH EN H 




SH EN H 



^ — O 



(COMPLEMENT) 



(SHIFT) 




COMP + SH H 



DB 00 
C 



SH DTB H 



[WRITE DATA, WRITE ALL, WRITE TIMING) 



(MOVE, SEARCH, READ DATA, READ ALL) 





TO DTB L 



(WRITE DATA, WRITE ALL, WRITE TIMING) 



Figure 3-9 Data Buffer 



WR EN(t) H 




D 1 

WB 00 
C 



-f — C 



TO 



G888> TRANSPORT 
>^ — WRITE HEAD 



WBOO (1 )H 



WB 00(1 )L 




TM EN H 



TO ^ 

TRANSPORT] USED 
MARK \ DURING 

TRACK f FORMAT- 

HEAD J TING 



VJ 



COO(0)H 



WREN(0)H- 



C00(1)H 



WREN(0)H 
TP01H 

WREN(1)H 
TPOO A H 
C01 (0) H 

MC02(1)H 
ST REV CK(1)H 

LPBOO(0)L 
LPBOKOL 

LPB02(0)L 
LPB03(0)L 
LPB04(0)L 
LPB05(0)L 



>^ 



^> 




RD EN LPS 00-02H 



-T_>^> 




RD EN LPB 03-05 H 




RD 00(1 )H- 
WRENd )H 
WBOO (1 ) 




::^=o 




RD00( 1 ) H ' \ \q_ 

WRENd )H \ \J ^/ 



DTB00(1)H 



XOR TO LPB H 



TO LPB L 



LPB NOT EQ 1H 



READ DATA H 

ST CK (1)H 
MC 00 (0) H 



r> 






XOR LPB 
03-05 



J I 

LPB 03 
K 



XOR LPB 00-02 



PARITY 

ERROR 

FLAG 

) I 

PAR 



~_y — t>^ir 



J I 

LPB 00 
K 



TO EF 



Figure 3-10 The Longitudinal Parity Buffer 



I/O RWCO H — 



r 



+ 3V 



I/O ADDR 
ACC(0)H- 



+ 3V- 



JT^ 



XSTA- 



D 1 

WC 
C 




PWR C 



LR L— c y 



D 1 

DF 
C 



1 TO DF H 




— C 

1-0 




FROld )L- 
(WRITE FUNCTIONS) 



SEARCH L- 
1/0 BRK RQ L 




— 



— c 



DTBOOd )L- 



DTBOKI )L- 



DTB11(1 )l 





— C 



I/O DATA IN H 

(DATA OUT WHEN LOW) 



1/0+1-^CA INH L 




DBOOd )L 



DB 01 (1 )L 



jo— DB 11(1)L 



I/O 8 BRK (0)H - 
+■ 3V- 



1/0 TS03L- 
+ 3V- 



FROKI ) H — 
(WRITE 
FUNCTIONS) 



M602 




CM1ir> — 1 +3H 



BMB00(1)H-i BMBOKDH-i BMBIKDH 



BMB TO DTB 




_Q_ 



It 

r 



DTB 00 



Jl. 



DTB 01 




DTB It 



Figure 3-11 The l/O Control 



When the computer uses more than 8K of core , It adds a memory extension control . In order to address more 
than 8K, the l/O Control uses a memory field register which is set by the program and supplies the current add- 
ress extension to Memory Extension Control Input EAOO L -^EA12 L. 



TIMING PULSES [ 
DF(I/0 BRK RQ L) 


PDP-8 
PDP-8I 


T1 
TP1 


T2 T1 
TP4 TP1 


T2 T1 T2 
TP4 TP1 TP4 


T1 
TP1 


T2 
TP4 


T1 
TP1 




/ 














I/O ADDR ACC (0) H 


\ 


















WORD COUNT 
STATE 


CURRENT ADDRESS 
STATE 


BREAK STATE 




I/O B BRK (0)H 




















1— 1 






I/O TS03 L BMB TO DTE 
FOR WRITE. ALSO DATA 
STROBE INTO MB FOR READ 
(BMB TO DTB) 






















DATA AVAILABLE FOR 
STROBING BY DEVICE 












I/O BWCO H 








r 






^ 








WCCWORD COUNT OVERFLOW 
FLAG) 



























Figure 3-12 The l/O Control Timing 

The DECtape (DTF) flag (Figure 3-13) is set at the end of each operation; this causes a program interrupt to the 
computer if the enable Interrupt flag (ENI) is also set. The DTF is reset with the XSTA lOT instruction. 
Engineering drawing D-BS-TC08-0-4 shows the logic which sets the DTF. 

3.2.1.8 The Write Enable Flag - One piece of logic which does not fit into any of the foregoing subsystems, 
but plays an Important role In the operation of the control. Is the WREN (Write Enable) flag (see Figure 3-14), 
which is set whenever the controller is writing Information on the tape. This flag enables the write amplifier; 
the conditions under which it is set are summarized in Figure 3-14. 

3.2.1 .9 The Status B Logic (see Figure 3-15) - The status B logic consists of the error flags (Sheet 1) and the 
memory field logic (Sheet 2). Table 3-2 summarizes the logical reasons for each of the errors. The functional 
significance is discussed in Chapter 2. 



3-19 



EFd) L 



-XSTA L 




— 




BACIUO) H — 



POWER CLEAR 



Figure 3-13 The DECtape Flag 



WRTM- 



SWTM 



UTS(1)H- 
WRITE OK H- 



WRITE ALL H- 



j—C D 1 
W-1NH 



C 



_r° 



D 1 

WC 
XSTAHC 



WC(1)H 



TPOOH 
C01(0)H 
MKT(O) H- 




( LOAD STATUS A lOT) 
I/O 
BWCO H-\ 



+ 3- 



ry 



DATA ( 1 ) L 

STCK(1)L 

ST FINAL (1)L 



i> 



DF(0)l 
WRITE ALL 



W-1NH(0)H 



EN 



On 




DTF(0)H — 
WRITE DATA H — 



ST DATA H 



rv 



MKT (O)H-C 



NOTE: 

WR EN IS SET UNDER THE 
FOLLOWING CONDITIONS 

1/ DURING"WRITE TIMING AND MARK" 
PROVIDED THE TAPE IS UP TO SPEED 
AND A TRANSPORT IS SELECTED. 

2/DURING"WRITE ALL" PROVIDED THE 
WORD COUNT DID NOT OVERFLOW OR 
THE DF FLAG WAS NOT SET. 

3/ DURING"WRITE DATA"PROVIDED ONE OF 

THE THREE DATA STATES, DATA ST 

CK AND ST FINAL ARE UP AND THE 

DTF HAS NOT SET. ( WHICH IS WHEN 

"WRITE DATA"WANTS TO WRITE DATA) 

4/ W-INH INSURES THAT THERE IS VALID 
DATA IN THE BUFFER BEFORE WR EN 
SETS. 



Figure 3-14 The Wrife Enable Flag 



3-20 



Table 3-2 
The Error Flags 



Flag 


Function 


Conditions When It Is Set 


MKTK 


MARK TRACK ERROR 


This error occurs if the window register decodes a 
MK BLK START, a MK DATA, a MK BLK END, or a 
MK END during any other but BLK MK or IDLE states, 
unless the transport is in a move mode. 


END 


END OF TAPE 


When the MK END code shows up in the window 
register, it signifies that the tape has gone into the for- 
ward end zone. This flag is posted. 


SEL 


SELECT ERROR 


A select error occurs under any of three conditions: 

(1) If the write timing and mark track function 
and the SWTM switch are not selected or un- 
selected simultaneously. 

(2) If a write function (FRO 1(1)) is selected by 
the v/rite enable switch and is not selected on 
the transport (-WRITE OK). 

(3) If no transport is selected; i .e., if no 
select switch of a transport corresponds to the 
number in the unit select register, or if more 
than one is selected. Both of these conditions 
are sensed by the G879. 


PAR 


PARITY- 


If, during a read operation (READ DATA), the LPB is 
not equal to one when ST CK occurs, then PAR is set. 


TIM 


TIMING ERROR 


A timing error occurs under any of the following 
conditions: 

(1) If a + 1 to DTF occurs while the DTF is 
still up. Indicating that the flag was not ser- 
viced In time . 

(2) If the data flag Is on a one when a shift 
data buffer pulse (SH DTB) occurs, indicating 
that the three-cycle break did not operate on 
time . 

(3) If an XSTA lOT occurs in any state other 
than BLK MK or IDLE, and the RD + WD signal 
is high, then the lOT occurred during a read or 
write operation, which should not happen. 



3-21 



r 



ERROR FLAG 
LOGIC 



PWR CLR 



h. 



MKTK(I) L 
TIMd) L 
ENDd) 
SEL(I) 



~^^ PARd) L - Q ^ y \y^ I p- IMOO L 



r<^^ y 



MARK TRACK 
ERROR FLAG 
LOGIC 



ST BLK MK(0)H 



MK BLK START L 

MK DATA L 

MK BLK END L 

MKENDL 



ST IDLE(0)H — 
cMOVEH — 




>- 



MCOKl) H - 



D 1 
MKTK 
C 



-c 



> 



1M01 L 



J 



END OF TAPE 
ERROR FLAG AND 
CLEAR LOGIC 



XSTAL 



OTO 



^ y ^"°" 



rr. 




IM02 L 



1 



SELECT ERROR 
FLAG LOGIC 



WRTMH 
-SWTM 
-WRTM 

SWTM 

FROKDH 
-WRITE OK H 

T SINGLE UNIT L 

XSTAL 
CSTAL 






[> 



sEL 




G^O- 




5pS DELAY 



-Q D 1 

SEL 



He ojo 



+-0 



> 



IM03 L 



PARITY ERROR 
FLAG LOGIC 



h 



READ DATA H — 
PB NOT EQ1 H — 




ST CK(1) H — 
MCOO(O) H — 



r>^ 



D 1 
PAR 

c o|o- 



-c 

K3 



TO SHEET 2 



> 



IM04L 



1 



Figure 3-15 Sfatus B Logic of the Error Flags {Sheet 1) 



3-22 



FROM SHEET 1 



TIMING ERROR 
FLAG LOGIC 



•XSTA L 



rf> 



\- 



^y_y[ 



M602 



DF(1)H — N. 

H DTB H - I ^ ^~_J y ^/*^ 

MK(0) H — j >. pQ! ^ "^ Ci 

)LE{0)H— V, r^-r.-,,^ u HTV 

^_L»,^^ u_ P"-" DTF(1) H — D 1 



ST BLK MK(0) H • 



STIDLE{0)H — 
RD+WD H — 



y 



TIM 
1 TO DTF H — I C 



T 



MEMORY FIELD 
LOGIC 



I/0BAC06(1) 



"X>^ 



I/O BAC07(1) H 



H~y — "^ 



I/O BACOSd) 



76 L 
77L 




""_>-^ 



76+77H 



I0P2H 



I0P4 



I/O BMB03(1) H - 
I/O BMB 04(1) H - 
I/O BMB 05(1) H - 
I/O BMB 06(1) H - 
I/O BMB 07(1) H - 
I/O BMB 08(1) H - 



_) 



77H 






DTSFH 



RSTBH 



"tlX 



LDMFH 



D 1 



c op 



D 1 
MF01 
C 



D 1 
MF02 

C oD- 






1~V 



DTF(1)L- 



< 



--C 



> 



77 



Figure 3-15 Status B Logic of the Error Flags (Sheet 2) 



IM05 L 



^ 



J Jo- EAOO L 



r> 



> 



IM06 L 



EA01 L 



IM07L 



EA02 L 



^ y 



JQ- IM08 L 



L> 



IM11 L 



J 



08-0459B 



3-23 



3.3 THE TC08 SYSTEM TIMING 

In the previous section, each of the individual subsystems of the TC08 controller was studied. In this section, 
these units are examined as they relate to the system. Extensive timing diagrams in Figures 3-16, 3-17, and 
3-18 show how the system behaves when in Write Timing and Mark Track mode, in Search mode going into 
Write or Write All, and in Read or Read All, respectively. 

3.3.1 Write Timing and Mark Track 

When the DECtape controller is set to this mode and the appropriate switches are set in the controller and the 
transport, the following events take place (see Figure 3-16). The Timing Generator begins to write the timing 
track and to generate TPOO and TPOl . COO and COl and MKT count. The WREN flag is set, and the data buffer 
circuitry starts to shift data into the word buffer. The DF is set, and the correct mark track coding is placed 
into the data buffer, after which the word buffer is shifted and complemented and the mark track is written 
(because TM EN H Is asserted). The Data Flag (DF) is set every four clock pulses to demand another word, and 
the DECtape Flag (DTF) is set either with the Data Flag, in normal mode, or after the word count overflows, in 
continuous mode. 

In this way, the timing and mark tracks are written onto a reel of magnetic tape. The codes which must be 
loaded into the data buffer are explained in Chapter 2. The program which does it is called TOG-8. 

3.3.2 Search and Write Data or Write All 

Figure 3-17 shows a timing diagram during a search operation which is followed immediately by either a write 
data or a write all function. During search, the data buffer is continually sampling the data tracks on TPOl . 
As soon as the forward block mark number is detected in the data buffer (at MK BLK MK time), the Data Flag 
is posted and the number is transferred into the current address register. The computer then switches the con- 
troller to WRITE DATA or WRITE ALL mode. In either case, the WR EN (Write Enable) flag is set, the Data 
Flag (DF) requests a 12-bit word from Memory through the 3-cycle break logic, and writing begins. 

The logic shifts a 3-bit word into the word buffer at TPOO time, and it complements this word buffer at TPOl time 
with the signals SH DTB and COMP + SH H. Simultaneously, the LPB is cleared, and it reads the last two lines 
of the Reverse PCC Mark cell . The LPB then proceeds to calculate its parity checksum from the data buffer as 
the writing continues. At the end of the block, the parity register is transferred into the data buffer by the LPB 
LPB-to-DB signal . This checksum is then written into the first two lines of the PCC Mark cell . If the controller 
is in Write Data mode, then the data flag does not set again, and the WR EN flag resets. In Write All mode, 
however, the WR EN flag remains on and the controller requests another data word every four lines. 



3-24 



CO 

I 



CLOCK 
PULSE 


- 


83 


U.SEC 


n n n 


n 


n 


n 


n n n n n 


n 


n n 


















CKOKI) 






1 




1 








1 




^_ 












CKOOd) 


L 


1 


^ 


1 1 1 


1 
n 










n 


TPOO H 
{MASTER CLOCK) 




n^ 


\r 






nl 


n 




n 






n 


n 




TP01 H 
(HALF CLOCK) 
















r- 


COOd) 


n 








1 
















C01 (1 ) 




1 






1 


1 








MKTd ) 






1 








1 












WR EN 




ASSUME WR EN WAS SET 


EARLIER BY 


MKT(0)H 


n 






1 


TO DTB 


DF 
(OR DTF) 




n 


POATA TRANSFERED HERE 


^ 










BMB TO DB 








-SH EN H 






1 


L_ 


1 


1 1 


1 


n 






n 


n 




n 


SH DTB H 


n 


n 


n 




D 


n n 


n 


n 


COMP+SH H 












/ 

WORD BUFFER 

COMPLEMENTED 

HERE 


SECOND BIT 
IN WORD 


/ 

comple:mented 
buffer here 



Figure 3-16 Write Timing and Mark Track Timing Diagram 



The DECi-ape flag (DTF) sets with the data flag (DF) during normal search, but only at the end of the word count 
during continuous search. In Write Data and Write All modes, the DECtape flag (DTF) sets at the end of each 
block during normal search, but only after the word count overflows during continuous search. 

Each of til© signoiS Oi Figure 3=i/ suouid ue examineu careiuny. Note that a write operation must oe preceded 
by a search operation in order to ensure that the counters are properly synchronized and that the correct block 
is written into. 

3.3.3 Read Data and Read All 

Figure 3-18 shows the system timing for the TC08 in Read Data or Read All modes. During these operations, the 
data buffer and longitudinal parity buffer (LPB) continuously sample the tracks during TPOl times. The Data 
Flag (DF) is posted as soon as the first 4 lines have passed after the state generator moves into DATA, and every 
four lines thereafter. The Data Flag stops when ST FINAL is removed during Read Data, but continues during 
Read All. 

At ST CK, the LPB tests to see if it has all ones, and posts a parity error flag if it has not. Parity is not de- 
tected during Read All . 

3.4 MOVE 

The move operation does not cause any significant operation within the controller except to detect the end of 
tape and post the appropriate error flag. This happens only if that particular tape transport is selected when it 
runs out of tape. (Note that a tape can be selected, set in motion, then deselected, and it will remember to 
keep moving.) 

3.5 TC08 VERSUS TC08N 

As noted in the opening paragraph of Chapter 3, the only difference between the TC08 and the TC08N involves 
level conversion. The TC08N is designed to be run on the negative logic PDP-8 computer. Modules designed 
to convert the negative logic to the positive levels available in the controller, and then the reverse, are plug- 
ged into the TC08. Prints number TC08-N-n and TC08-0-1 show these differences. 



3-26 



I I I I I I 1 I 



!!!!!!!!!l!!!!l!!!lll!lllllll!!l!l!llll!llll! 



I M I I I ! ! ! ! ! ! 



SEARCH MODE 



TAPE MOTION 



^ 



REV END 

MARK 

55 



REV END 

MARK 

55 



INTERBLOCK 

SYNC 

25 



INTERBLOCK 

SYNC 

25 



rOKWAKU 

BLOCK 

MARK 

26 



REVERSE 

GUARD 

MARK 

32 



LOCK 

MARK 

10 



REVERSE 
PCC 
MARK 
10 



REVERSE 
FINAL 
MARK 
10 



REVERSE 

PREFINAL 

MARK 

10 



WRITE DATA 



DATA 

MARK 

70 



REVERSE REVERSE 

DATA PREFINAL FINAL PCC LOCK GUARD BLOCK INTERBLOCK INTERBLOCK 

MARK MARK MARK MARK MARK MARK MARK SYNC SYNC 

70 73 73 73 73 51 45 25 25 











































10 1 10 1 


10 1 10 1 


10 10 1 


10 10 1 


10 1 10 


110 10 


10 


1 


10 


10 


11 10 


1110 


1110 11 


1110 11 


1110 11 


1 i i 1 1 


10 1 1 


10 1 T" 


10 10 1 


10 10 1 










3 6 9 

1 4 710 

2 5 8 11 






3 

1 4 

2 5 


3 6 9 3 

1 4 7 10 1 4 

2 5 8 11 2 5 


6 9 

7 10 

8 11 


3 6 9 

1 4 7 10 

2 5 8 11 


3 6 9 

1 4 7 10 

2 5 8 11 


3 

1 4 
25 


6 9 

7 10 

8 11 


3 6 9 

1 4 7 10 

2 5 8 11 


3 6 9 

1 4 7 10 

2 5 8 11 


3 

1 4 

2 5 


6 9 
710 
811 


3 6 9 

1 4 7 10 

2 5 8 11 















TPOOH 



TPOIH 

COOd 

COKI 

MKTd 

M 000(1 

MC01 (1 

MC02(1 



_jiLnjnjnjiJiJinjiJijriJxrLj~LJ^^ 
jijiji_ririJTJiJTrLJ~LJiJiJiJiJ^^ 




'U^U^U^U U LTU I 



n 




SYNC H 



MK- Qi k-Mi/ WK DATA 
MK BLK MK SYNC 



WiNDO'A' REGISTER DECODING 
STATE REGISTER 

WR EN{1) 

TO LPB 
LPBTO DB 



725 525 525 525 525 525 525 526 
en czi czi en cn t=\ CZ3 c=n 



IDLE 



2. 






MK BLK 


MK BLK 


MK BLK 


MK BLK 


START 


START 


START 


START 


610 


410 


410 


410 


CZl 


ra 


CZl 


era 



MK DATA 
470 



ST BLK MK 



I ST REV CK 



MK DATA 

470 

cn 



MK BLK 
END 
473 
-nzi 



MK BLK 

END 

773 

■'cn 



DATA 



I ST FINAL IsTCkF 



MK BLK 

c M n 

773 
cn 



MK BLK 
END 
773 



751 

CID 



545 

CZ] 



525 

CZl 



525 

IZZI 



IDLE 



XOR LPB 



[03- 
|00- 



05 
02 



DF 

DTF 

TO 0TB 

SH DTB 
SH EN H 

COMP+ SH H 
WR EN (1) H 



f00-02 



-05 



DF 
TO DTB 

COMP+SH H 
SH DTB 



^ 



t°I°_!-P^^ 



n BLOCK NUMBER 
I I TRANSFERRED 



DTF INDICATING 
'BLOCK NUMBER 



.RESET 
BY lOT 



HAS BEEN TRANSFERRED 




DTF FOR NORMAL, FOR CONTINUOUS THE WORD COUNT MUST HAVE OVERFLOWED 



LMJiriilMIlJ¥irLllIiriIli¥LAJU^ 




in) 



nAnAnjJAnAn.n^n^nMn.n^n^nji^n^n^njiji^njiji^mn^^^^^ 



STARTS WITH WRITE DATA MODE- 




I 



Figure 3-17 Timing Diagram for 
Driving Search Write Data or Write Al! 



3-27 



JP->\ 

JIOTION_^/ 



REV END REV END INTERBLOCK iNTERBLOCK 

MARK MARK SYNC 9YNC 

55 55 25 25 



FORWARD 


REVERSE 




REVERSE 


REVERSE 


REVERSE 


BLOCK 


GUARD 


LOCK 


PCC 


FINAL 


PREFINAL 


MARK 


MARK 


MARK 


MARK 


MARK 


MARK 


26 


32 


10 


10 


10 


10 



DATA 

MARK 

70 



DATA PREFINAL FINAL PCC 

MARK MARK MARK MARK 

70 73 73 73 



REVERSE 




REVERSE 




LOCK 


GUARD 


BLOCK 


INTERBLOCK 


MARK 


MARK 


MARK 


SYNC 


73 


51 


45 


25 



INTERBLOCK INTERBLOCK 

SYNC SYNC 

25 25 



22 



22 

















































10 110 1 


10 110 1 


1 1 1 


10 10 1 


10 110 


110 10 


10 


1 


1 


10 


11 10 


11 1 


11 10 11 


1110 11 


1110 11 


1110 11 


10 10 1 


10 1 1 


10 10 1 


10 10 1 


10 10 1 


1 1 


1 f 










3 6 9 

1 4 7 10 

2 5 811 







































.32;isi30% 



TPOOH 
TP01H 
C00(1)H 
COKDH 

MKT(1)H 
MC00(1)H 

MC02(1)H 



I I I I I I I I M I M I 1 I M I I M I I I I I I M I I I I I I I I I I I I I I I I! I I I I I M I I I I M I I M I I M LI t M I I I I I I I I M 



xiJin_rLnjnJxru~u"LrLru~u~u~u~LJ~u"u"u^u"u"u"u"u^^ 
jijiiTnj~iJTjriJiJiJTJTJiJiJiiirLJTJi^^ 

, — ^__, — L^ — L_. — 1^ \ — L^ — L_, — L_. — L. — L_ — L — L — L_^ — !__. — ^-J — L — LJ — L^ — L^l — L^l — L^ — L — L_ — L_ — L_i — L_l L 

n I \ \ L 



WINDOW REGISTER DECODING 



STATE REGISTER 



JTJTJUinJIJ 



1 1 1 I 1 

I 1 I 1 L 



-I I 1 1- 



1 1 



_l L. 



I I I I I I 



_l l_ 



1 r 



1 1 



J 



J L 



SYNC H*- 



MK BLK MK 



725 525 525 525 525 525 525 526 

izzinzicinimcnizziciziczi 



MK DATA 
SYNC 


MK BLK 
START 


MK BLK 
START 


MK BLK 
START 


MK BLK 
START 


MK 


632 


6t0 


410 


410 

CZ2 


410 

CD 


470 



MK DATA 
470 



MK BLK 


MK BLK 


MK BLK 


MK BLK 




END 


END 


END 


END 




473 


773 


773 


773 


751 


cn. 


l=lv 


1=1 


cm 


izn 



545 



525 

IZZI 



1 r 



525 



622 



622 



622 



a I BLK MK I ST REV CK | 



ST FINAL ISTCK 



qx irii ^ 



TO LPB 



TO LPB 



RDEN LPB 00-02 
XOR LPB 00-02 
RDEN LPB 03-05 
XOR LPB 03 -05 
-SHEN H 
SH DTB 

DF (REQUEST DATA TRANSFER) 
DTF 



DF REQUEST DATA TRANSFER 8 
DTF WHEN ON NORMAL MODE. ON 
CONTINUOUS MODE DTF SETS 
WHEN THE WORD COUNT 
OVERFLOWS. 



UUULILJUULJU 



ULJI_ll_IUUUI_IUl_iLJLJI_l 



LJ LJ LJ L_l LJ l_l 



j"iJiJTJiJTriJiJij~m_rLri_rLJi_rij~ 



"ii~ir~ii — irni—irni — ii — irnrnrni—i 

LJLJLJLJLJLJLJLJLJLJLJLJL 



READ DATA 



LiiJiMJijmrLimnMJinjinjiJinj^ 



1 1 



1 1 1 1 1 1 1 1 1 



I I I [ I M! I I I I I I I I I I I I I I M I I 



J DTF( CONTINUOUS MODE) L 
(WHEN WC OVERFLOWS) 



RESET BY lOT 



DTF IF NORMAL MODE 



RESET BY lOT 



-iRESi 



PARITY FLAG IF PARITY ERROR 






END FLAG 



I I I I I ! I I I 1 I 1 M I ! 1 I 



M,,,, !,.,,! 



I I I M I M I I I I II II I i I I I ! iM ! M ! i I I I I I I M M M M i I M M N I iM i I I 1 i 1 I I . I I I i J I I I I II M I I M I M I i M i ; I I I ( I I II :M M Ii I Ii I M mM II i M' ; I ^ M M I I : M 
'NOTE: THAT SYNCHRONIZATION OCCURS AT EACH INTERBLOCK SYNC ON READ DATA, BUT ONLY AT THE BEGINING OF THE FIRST BLOCK DURING READ ALL. 



h,,.!,,,,! 



I H ! M I I ! I I I I ! I I I I ! M ! I I I I i I M I I I I ' I I M I I I ! M M I M I I I I I I ! I I! I i M I M I I ! ! h ■ ■ I 



Figure 3-18 Timing Diagram 
for Read Data and Read All 



3-29 



CHAPTER 4 
INSTALLATION 

This chapter provides installation instructions, including unpacking and intercabling instructions, and space, 
loading, power, and environmental requirements, as well as preliminary checks which should be performed before 
the equipment is energized and initial turn-on and checkout procedures to ensure that equipment is properly 
installed. 

4.1 UNPACKING 

4.1.1 Hardware 

Packaging can vary over a wide range, depending on the system configuration ordered by the user. For example, 
if the user has ordered an entire PDP-8 System, the TC08 is shipped installed in its appropriate rack (see Figure 
4-1), together with the required cables. If a whole system is shipped, the interconnecting cables are installed. 

If, on the other hand, only a part of a system is shipped because the user already has a programmed data 
processor, the DECtape system may be shipped separately, but with the cables. Unpack the equipment as 
follows: 

a. Place the equipment package within the installation site near its projected location. Cut the ship- 
ping straps and remove all packing material . 

b. Open the rear doors, remove the shipping bolts which hold the plenum door closed, and open the 
plenum door. Remove the machine screw which holds each side of the cabinet to the pallet. Slide the 
cabinet off the pallet, using a ramp (approximately 4 3/4 inches high) from the floor to the top of the 
pallet. Move the cabinet to its final location within the installation site. 

c. Remove the tape which holds the modules in place within the mounting panels, and the tape which 
holds the power and interconnecting cables to the floor of the cabinet. 

4.1.2 Software 

Each DECtape system is shipped with the software required for installation. This diagnostic software includes 
punched paper tapes, a description of the program, and a listing. Table 4-1 lists the software for the TC08. 



4-1 



FRAME PANEL 
(H950-LA) 



COVER PANEL 
(H950-P) 




FAN ASSEMBLY 
(H952-CA) 



MTG. DOOR PANEL 
(H950-DA) 



SHORT DOOR 
(H950-HA thru HK) 




END PANEL 
(H952-AA) 



FULL DOOR 
(H950-BA) 



Figure 4-1a H950 Frame 



4-2 



FILTER 



FRAME 
(H950-AA) 



FILLER STRIP 
(H952-GA) 



MOUNTING HOLES 
18-5/16" CENTER 
TO CENTER ALL 
SIDES 



{H952-BA) 
STABILIZER FOOT 
(TWO REQ) 




(7406782) KICKPLATE 



(H952-FA) LEVELERS 



2-21/32 



(H952-EA) 
CASTER 



Figure 4-1 b H950 Frame, Dimension Diagram 



4-3 




Figure 4-2 DECtape System in Cabinet 



4-4 



TC08 Software 


TC08 BASIC EXERCISER 


MAINDEC-08-D3BB-D 


TC08 DECTAPE FORMATTER 


DEC-08-EUFA-D 


TC08 DECTREX 1 


MAIN DEC -08-D3RA-D 


TC08 EXTENDED MEMORY EXERCISER 


MAINDEC-08-D3EB-D 


TC08 LIBRARY SYSTEM 


DEC-08-SUA1-LA 



4.1.3 Inspection 

Inspect all of the equipment before installing it, checking each piece against the parts list of print TC08-0-15 
Table 4-2 lists the cables supplied with a complete system. Any damage must be reported immediately to the 
shipper and the DEC representative. 

Table 4-2 
DECtape Cables 



Type 


Standard Length 
(Ft) 


Number 


Use 


BC08 


8 


5 


I/O Bus and 3-Cycle Break 


W023 - W023 


4 


1 per TU55 transport 


Command Cable 


M908 - M908 


4 


] per TU56 transport 




W032 - W032 


4 


1 per transport 
(TU55 or TU56) 


Head Cable 


Indicator Cables 


5 


4 


Indicator Panel 



4.2 SPACE AND ENVIRONMENTAL REQUIREMENTS 

4.2.1 Space Requirements 

Figures 4-1 and 4-2 show the clearances required for the DECtape system installed in the PDP-8, 8/l, and 8/L 
free standing cabinets. When installing the system, be sure that front and rear of the cabinets are accessible to 
maintenance personnel . If the cabinets are separated by long distances, consideration should be given to over- 
head trenching ducts or floor ducts for the cabling. 

4.2.2 Environmental Requirements 

The manufacturer of the magnetic tape recommends that the equipment be operated in a temperature range of 
60° to 80°F within 40 to 60% relative humidity. 



4-5 



4.3 POWER REQUIREMENTS 

4.3.1 Power Supplies 

Power for the operation of the TG08 controller is derived from a standard DEG power supply type 783 or equiva- 
lent. The TG08 uses approximately 1/4 of the capacity of the supply. This power con be shared v/ith existing 
783 power supplies already installed in the cabinets up to the limits of their respective capacities. The 
characteristics of the power supply are given in the Logic Handbook. It is designed to mount on the plenum door 
of the standard 19-inch rack . Power requirements for the TU55 and TU56 transports are given in their respective 
Maintenance Manuals. 

The indicator panel is powered with a 716 Indicator Supply. Its characteristics are summarized in Ghapter 6. 

4.4 TG08GABLING 

4.4.1 Gabling the TG08 to the Gomputer 

The TG08 should be connected to the PDP-8, 8/l, or 8/L I/O Bus and 3-cycle data break facility. Table 4-3 
lists each cable and where it interconnects. All 5 cables are type BG08 bus cables (see Figure 4-3). 



Table 4-3 
TG08 or TG08N to The PDP-8, 8/l, or 8/L Gabling 



I/O Signal Name at TG08 


TG08 
Location 


Location 
in Gomputer 


Out 


In 


8 


8/1 


8/L 


I/O BAG 00(1 )H - I/O BAG 08(1 )H 

I/O BAG 09(1 )H - I/O PWR GLR H 

I/O BMB 00(1 )H - I/O BMB 05(1) H 

I/O BMB 06 (0)H - I/O BMB 11(1)+1 

IM 00 L - IM08L 

IM 09 L - I/O B - RUN(0)L 

DATA 00 - DATA 8 

DATA 09 - I/O ADDR AGG H 

DB00(1)L -DB08(1)L 

DB09(1) -EAOOL 


D02 
D02 
D03 
D03 
D04 
D04 
D05 
D05 
D06 
D06 


A02 
A02 
A03 
A03 
A04 
A04 
A05 
A05 
A06 
A06 


ME34 

ME35 

MF34 

MF35 

PE2 

PE3 

PE3 

PF3 

PE4 

PF4 


JOl 
J02 
J03 
J04 
J09 
JIO 
J06 
J06 
J07 
J08 


D36 
D36 
D35 
D35 
D34 
D34 
G36 
G36 
G35 
G35 



4.4.2 Gabling the TG08 to the TU55 or TU56 Transports 

The TG08 is cabled to each of the transports on a 2-cable parallel bus system, shown in Figure 4-3. Table 4-4 
summarizes the use and location of each cable. 



4-6 



PDP-8 



I/O BUS (5 CABLES BC08) 



N OUT IN OUT 



PERIPHERAL 
#1 



PERIPHERAL 
#2 



IN OUT 



TCOB 



5 CABLES 



TCOB 
INDICATOR 
ASSEMBLY 



2 CABLES 



TU55 



rW032-W032 
tw023-W023 



2 CABLES (^°f-i:;023 
I M908-M908 



TU56 



2 CABLES (*023-W023 
(_M908-M908 



TU55 



Figure 4-3 DECtape Cables 



Table 4-4 
Cabling Behveen the Controller and Transports 



Signal Name and Location at TC08 


TU55 


TU56 


Cable 
Type 


In 


Out 


In 


Out 


Cable 
Type 


TGO L - TOO L A24 


W023- 
W023 


A05 


A06 


A06 


A07 


M908- 
M908 


Read/A^rite Heads A,B19 


W032- 
W032 


A,B02 


A,B03 


A, BIO 


A,Bn 


W032- 
W032 



4.4.3 Cabling the Display Panel 

Table 4-5 summarizes the signal cabling between the TC08 controller and its display panel. 



4-7 



Table 4-5 
Cabling Betv\«en the Controller and Display Panel 



Signal Names on Indicator Panel 


TC08 Location of M916 Connector 


USR - MF 
DTB - LPB 2 
MF 1 - MC 2 
LPB 3 - WTM 


A25 
A25 
A26 
A26 



The connectors are M916 boards at the TC08, hard wired into the indicator assembly at the other end. The 
cables are about 5 feet long. 

4.5 FINAL CHECKOLTT 

After the system is installed, cabled, and powered, it must be made operational. The available tools are the 
diagnostics, a scope, the logic prints, and the engineer's knowledge of the system. 

Final checkout can be approached in one of two ways. The preliminary checks, such as testing for power clear 
operation, resetting all delays, and checking for the proper operation of each transport, can be done as listed 
in Chapter 5; or else the field engineer con start directly with the diagnostics. It is recommended that he per- 
form the former, or at least check that all delays are set properly when the diagnostics run. It is important that 
Chapter 5 be consulted during this period. 



4-8 



CHAPTERS 
CHECKOUT AND MAINTENANCE 

This chapter presenh the mamtenance concept of DECtape, followed by some notes on troubleshooting. The 
procedures recommended to assemble a TC08 controller are outlined together with TC08 calibration and diag- 
nostics. This chapter assumes that the reader is familiar with Chapters 1 - 4. 



There are only two rules to be followed if the TC08 is to be properly maintained: 

1 . Carry out the preventive maintenance routines regularly. 

2. Always perform a complete checkup on the equipment after troubleshooting a particular fault. 

The reasons for the first rule are obvious. Unless cables, wiring, panels, and modules are regularly checked for 
mechanical problems and unless the heads are free of dirt and the tape is properly handled, even the most re- 
liable tape system will fail . 

The reason for the second rule is less obvious. It is important that a DECtape system be completely tested during 
any troubleshooting because the system is so reliable that borderline faults may not show up until later. Check- 
ing all parts of the system may reveal marginal problems that can be repaired immediately. Unless a thorough 
examination is performed, these faults may occur shortly thereafter, needlessly shortening the mean time be- 
tween failures on the system. 

5.2 TROUBLESHOOTING THE TC08 

Everybody has his own style of troubleshooting equipment he knows well . If it is an effective approach, it 
begins with a thorough check of the most obvious problems; whether the power is on, all cables properly 
connected, all modules plugged in, and all switches, dials, lights, etc., in their proper state. 

The next step is to define the problem, which also involves locating it. Is the computer, the controller, or the 
transport at fault? Can ony one or all be replaced with working equivalents? Usually a system has more than 
one transport, so that the responsiblility of that unit is easily defined. If the computer is failing, other 



5-1 



peripherals will usually have problems. Once the problems have been located in the controller, a similar pro- 
cedure should be used to locate the subsystem within the unit (the module) which is at fault. An interesting 
approach is to record a series of relevant inputs and outputs; then, using the prints and the reading, try to 
correlate the various symptoms with a possible cause. This usually leads to speculation, more tests, and a 
solution. 

Once the fault is located, the controller should be given a complete examination. All diagnostics should be 
run, and all delays and the clock properly set up. 

The biggest secret to efficient troubleshooting is a thorough knowledge of the machine and of the diagnostics 
which test it. The TC08 is described in this manual; the diagnostics are described in their respective publica- 
tions. 

5.3 TC08 ASSEMBLY 

Before the TC08 is assembled, certain preliminary checks must be performed to avoid damaging the entire unit. 
These are outlined below. The need for this procedure usually occurs in the factory, although there may be 
occasions to use it in the field. 

5.3.1 Equipment 

In order to assemble a TC08 or TC08N control , the following equipment must be available. 

a . TC08 back panel 

b. TC08 indicator system 

c. TC08 or TC08N module kit 

d . TC08 and TC08N print set 

e. TC08 Maindecs (also called TC01 Maindecs) 

f . 738 power supply or equivalent 

g. 716 indicator supply 

h. A minimum of 1 TU55 or TU56 transport 
i . A dual trace scope 



5-2 



The procedure for assembling a TC08 or TC08N control is as follows. 

a. Inspect the module mounting panel for such mechanical problems as power bus breaks or shorts 
(usually caused by loose solder or wires), bent or pushed-in pins, broken blocks, and broken wires. 
Check that the WRTM/NORMAL switch is properly installed. 

b. Plug the G821 power regulator card into its slot as shown on the module map of print TC08-0-13. 
Connect the POWER OK indicator across pins BOl M2 and BOl Ml . 

c. Connect Power from the 783 power supply to the regulator with the Mate-N-Lock connector. Turn 
on the 783 and check all power busses in the empty panel. Table 5-1 shows the voltages to check. 
Turn off the power supply at the end of this test. 



Table 5-1 
Voltage Test Points 



Pins 


Correct Voltage 


A2 
C2, Tl 


+5V 
GND 



d. Connect the 716 power supply to the indicator system. Install the indicator cables according to 
Table 5-2. Turn on power to both the panel and the indicators. All indicators except those which are 
deliberately tied to ground (i.e., all those without a name) should be ON. If some are not, repair 
them. Remove all power when this step is completed (see Figure 2-7). 



Table 5-2 
The Indicator Cables 



Signal Name 
at TC08 


TC08 
Location 


Display Panel 
Location 


Connector 
Type 


USR00(1)H - 
MF00(1)H 


A25 


USRO - MFO 


M916 - Hard 
wired 


DTB00(1)H - 
LPB02(1)H 


A25 


DTBO - LPB2 


M916 - Hard 
wired 


MF01(1)H- 
MC02(1)H 


A26 


MFl - MC2 


M916 - Hard 
wired 


LPB03(1)H - 
SWTM H 


A26 


LPB3 - WTM 


M916 - Hard 
wired 



5-3 



e. Plug in the modules according to the module map of print TC08-0-1S. Plug in the rest of the cables 
according to Table 5-3. 



Table 5-S 
Computer and Transport Cab! 



es 



I/O Signal Name 
at TC08 


TC08 
Location 


Location in 
Computer 


Out 


In 


8 


8/1 


8/L 


I/O BAC 00(1)H - I/O BAC 
08(1)H 

I/O BAC 09(1 )H - I/O PWR 
CLR H 

I/O BMB 00(1 )H - I/O BMB 
05(1) H 

I/O BMB 06(0) H - I/O BMB 

n(i)+i 

IM 00 L - IM08L 

IM09L- I/OB- RUN(0)L 

DATA 00 - DATA 8 

DATA 09 - I/O ADDR ACC H 

DB 00 (1)L - DB08(1)L 

DB 09 (1) - EA 00 L 


D02 

D02 

DOS 

DOS 

D04 
D04 
D05 
DOS 
D06 
D06 


A02 

A02 

AOS 

AOS 

A04 
A04 
AOS 
AOS 
A06 
A06 


MES4 

MESS 

MFS4 

MF3S 

PE2 
PES 
PES 
PF3 
PE4 
PF4 


JOl 

J02 

JOS 

J04 

J09 
JIO 
J06 
J06 
J07 
JOS 


D36 

DS6 

DSS 

DSS 

DS4 
DS4 
CS6 
CS6 
CSS 
CSS 


Signal Name and 
Location at TC08 


TU55 


TUS6 


In 


Out 


In 


Out 


TGO L - TOO L A24 
ReadAVrite Heads A,B19 


A05 
A,B02 


A06 
A, BOS 


B04 
A, BIO 


BJ7 
A,B11 



S.4 TC08 PRELIMINARY CHECKOUT AND CALIBRATION 

The following steps comprise the procedure for preliminary checkout and calibration of the TC08. 

a. Test power clear for correct operation by scoping the power clear input to all flip-flops and turning 
the computer on and off. A less rigorous test is to check if the indicators go off with power clear. 

b. Dial one of the transports to 8 or 0, and any other to different numbers. This is the transport that 
will be used for the test. 

c. To test all the lOTs, key in the following instructions. 



S-4 



Location 


K,oae 


mneumonic 


0000 


7604 


LAS 


0001 


0010 


AND (0017) 


r\r\r\r\ 


1 rti 1 


X A r\ t i-7tr\\ 


VA/UZ 


lUi i 


\f\U \0/0\J) 


0003 


3005 


DCA 


0004 


1012 


TAD (0400) 


0005 


7402 


HLT 


0006 


5000 


JMP START 


0007 


7402 


HLT ]/0 SKIP 


0010 


0017 




0011 


6760 




0012 


0400 





Start the program at location 0000, and set bits 8-11 into the switch register to select the lOT code 
that is to be executed. Table 5-4 shows what the switch register does. 



Table 5-4 
The Switch Reaister Bits 



Switch Register Bit 


State 


Code Selector 


8 





76 


8 


1 


77 




^9 


1 


IOP4 


Unselected, these 


10 


1 


IOP2 


bits do nothing ,, 


1 


lOPl 



This program executes the lOT instruction that is indicated in the switch register until it is halted. The 
lOT decoding should be checked by watching the outputs of the M103 decoders with a scope and then 
placing the correct code and control pulse into the register. 

d. Calibrating the TC08 controller involves setting up the various delays. The XSA DY delay shown 
in print TC08-0-6 can be triggered by placing 0004 into the switch register and starting the preceding 
lOT program. Set this delay to the value indicated in the prints. 

e. To fire the U & M DY delay, shown in Print TC08-0-3, key in the following program. This program 
causes the direction bit to be XORed at a rate determined by the contents of the switch register. Set 
the delay to the value shown in the prints. 



Start 



0000 


7604 


LAS 


0001 


7040 


CMA 


0002 


3015 


DCA 


0003 


2014 


ISZ 


0004 


5003 


JMP .-1 


0005 


2015 


ISZ 


0006 


5003 


JMP .-3 


0007 


1013 


TAD 


0010 


6764 


DTXA 


0011 


5000 


JMP START 



5-5 



0012 


7402 


HLT I/O SKIP 


0013 


0400 




0014 


0000 




0015 


0000 





f. Remove the G888 in slot A18 and add a temporary jumper between D14K2 and D14U1: then change 
address 13 of the previous program to ALL Zeros. The program may be used to fire the SP DY which 
should be set to the value noted on print TC08-0-3. Set - XTDY also. After these delays are set, re- 
move the jumper, insert the G888 back into slot A18, and replace the original contents of address 13 
(0400) . 

g. Add the following instructions to the previous program, to produce a tape-rocking program. Start 
this program at location 16. 

0016 7600 CLA 



0017 


1023 


TAD 


0020 


6766 


DTLA 


0021 


5000 


JMP START 


0022 


7402 


HLT I/O SKIP 


0023 


0200 





h. Use the following program to enable and calibrate the write timing and mark track clock. 

Start 0000 1004 TAD 

0001 6766 DTLA 

0002 0002 6764 DTXA 

0003 5002 JMP .-1 

0004 0260 

Place unit 8 on-line and write enabled. Place WRTM normal switch in the WRTM position. Start the 
program. The clock should be set to the value noted on engineering drawing D-BS-TC08-0-3. 



5.5 TC08 DIAGNOSTIC TESTING 

5.5.1 Diagnostics 

The controller is now calibrated. The following diagnostics should be run in the order indicated. 

a. The TCOl basic exerciser (MAINDEC-08-D3BB-D) or Extended Memory Exerciser (MAINDEC-08- 
D3EB-D) when applicable. 

b. DEC tape Formatter (DEC-08-EUFA-D) 

c. DECtrex 1 (MAINDEC-08-D3RA-D) 

d. The DECtape Library System (DEC-08-SUA1-LA) 

e. Elevated temperature testing. The control must run DECtrex 1 for one hour free at 55° Centigrade, 

f. Life testing. DECtrex 1 should be run for a minimum of one hour per transport. 



5-6 



5.5.2 Testing fhe Mark Track Decoder 

The most important single subsystem within the controller is the mark track decoder, which is contained within 
rne /vi^czo moauie. rrooiems wiTriuj ims wiuuuie ^^a^ wc mc iiiuai uimi^uii iw uiuyuose. 

a. The following procedure outlines a possible approach. It assumes that the controller can search. 

(1) Load the basic exerciser (MAINDEC-08-D3BB-D) into the computer. 

(2) Have the exerciser rock the tape in search mode. 

(3) Check the output of the mark track reader. 

(4) Check each window flip-flop to see if all are getting set. This can be done by examining the 

(5) Scope each mark track code. Compare the number of times the code appears against the format, 

(6) The timing pulses are also critical inputs to the mark track decoder. Thoroughly check the 
timing circuitry. 

b. If the machine cannot even search properly, check the following areas of possible fault. 

(1) Are the data flag and the DECtape flag being set properly? 

(2) Is the +1 ^ CA INH operating during search? 

(3) Are the breaks taking place in the right direction? 

(4) Is the break going to the proper address? 

(5) Is the machine performing a single-cycle break rather than a multi-cycle break? 

None of these tips can replace a thorough knowledge of the equipment, and a carefully controlled set of tests. 



5.6 DECTAPE PREVENTIVE MAINTENANCE 

Preventive maintenance involves visual inspection of the system according to the list in Table 5^5, running the 
diagnostics, and adhering to the practices listed below. 

5.6.1 Handling Magnetic Tape 

When tape is handled (during splicing), the operator's hands should be clean to prevent contamination of the 
tape by body oils and salts. The use of sticky masking tape or cellulose tape as splicing or tail-end hold-down 
is not recommended, because small deposits of the adhesive will strick to the tape. 

Heads and guides should be cleaned regularly to remove accumulations of foreign matter. 



5-7 



Table 5-5 
Visual Inspection Checklist 



Item 


Check 


Mechanical 
Connections 

Wiring and 
Cables 

Air Filters 

Modules and 
Components 

Indicators 
and Switches 


a. Check that all screws are tight and that all mech- 
anical assemblies are secure. 

b. Check that all crimped lugs are secure and that all 
lugs are properly inserted in their mating connectors. 

a. Check all wiring and cables for breaks, cuts, frayed 
leads, or missing lugs. Check wire wraps for broken or 
missing pins. 

b. Check that no wire or cables are strained in their 
normal positions or have severe kinks. Check that 
cables do not interfere with doors and that they do not 
chafe when doors are opened and closed. 

Check all air filters for cleanliness and for normal air 
movement through cabinets. 

Check that all modules are properly seated. Look for 
areas of discoloration on all exposed surfaces. Check 
all exposed capacitors for signs of discoloration, or 
leakage, or corrosion. Check power supply capacitors 
for bulges. 

Check all indicators and switches for tightness. Check 
for cracks, discoloration or other visual defects. 



5.6.2 Cleaning DECtape Reels 

If the tape is contaminated by dust, carefully wipe the surface and backing of the tape with a lint-free cloth, 
such as a very soft chamois. Contamination that does not brush off easily can be washed off with a cloth slightly 
moistened with Freon TF. Aliphatic hydrocarbon -type solvents (heptane, gasoline, naphtha) can also be used, 
but care should be exercised because they are flammable. Do not use carbon tetrachloride, ethyl alcohol, 
trichlorethylene, or other unknown cleaning agents because they may soften the oxide, deform the backing, 
or both. 



5-8 






The best method of storage is to place the reel of tape in a self-sealing plastic case supplied for the purpose by 
DEC, and store it on edge in a storage bin equipped with partitions between each two reels. The plastic case 
protects tape from dust and sudden changes in humidity and temperature. It also guards both tape and reel from 
damage in handling when the tape is transported between work and storage areas. 

If the tape must be stored in the presence of magnetic fields, either ac or dc, special containers are available 
which will protect the data from erasure in all but extremely high fields. It is more desirable to store them 
away from such fields, if at all possible. 

Avoid extremes of temperature and humidity. In general, recommended storage conditions are: 

Relative humidity: 40 to 60% 
Temperature: 60 to 80° F 

When extremes in temperature are encountered during storage or transit, tape should be brought to equilibrium 
before it is used. 

5.6.4 Physical Distortion 

Most signal dropouts in digital recordings are caused by specks of dust and other contaminants which lift the 
tape away from the head. However, two other significant causes are dents and creases in the base material. 
Dents are caused by particles wourd up tightly in the roll or by roughness in the surface of the hub on which 
the tape is wound. These may cause permanent dents or creases in many layers of the tape which cannot be 
stretched out flat as the tape passes over the head. Stresses in the roll which stretch the backing 5% will 
usually leave a permanent impression. Stresses below the 5% level are not usually permanent. Creases are 
caused by handling the tape (i.e. , threading, splicing, removing the tape from the guides, etc.) or by damage 
to the edges of the tape because of uneven winding. 

5.6.5 Accidental Erasure or Saturation 

The magnetic properties of instrumentation tapes are extremely stable. The magnetic retention is permanent 
unless altered by magnetic fields such as those generated by permanent magnets or electromagnets. These will 
probably cause partial erasure if placed within a few inches of the tape. 



5-9 



Both unrecorded and recorded tapes should be kept away from electromagnetic bulk erasers and storage cabinets 
with magnetic latches. Unrecorded tapes should not be placed near dc magnetic fields, such as traveling-wave- 
tubes or magetron magnets, because they may become heavily biased or even create gross distortion in the re- 
cord process (i.e., the resultant signal-to-noise ratio will be reduced). 

If parts of the recorder become magnetized, they can cause tape erasure, possible tape saturation, and signal 
degradation. As a preventive measure, periodic demagnetization of critical parts, particularly heads, is rec- 
ommended. 

5.6.6 Head Care and Head Life 

The following factors must be considered when maintaining tape heads. 

a. Cleanliness of tape, the transport, and their environment. 

b. Maintenance procedures which involve the checking of tape tension, tracking, etc. 

c . The abrasiveness of the tape being used . 

d. Solvents used for cleaning the heads. 

Cleanliness in and around the head area is of utmost importance in all tape machines. Dirt particles become a 
serious threat to the data "take" because they cause spacing loss. They can also become minute scrapers, 
gougers, and cutters to the head and tape surfaces when dragged between them. 

Care must be taken not to touch the heads with any metallic or hard object to avoid scratching, gouging, or 
magnetizing the heads. For cleaning the heads, use only alcohol, naptha, Freon TF, or gasoline. Freon TF 
is probably the best all-around cleaner. It should be noted that most head cleaners will also dissolve lubrica- 
ting greases and tape binders and should be used carefully, especially around bearings and the tape. Cotton 
swabs make good disposable cleaning tools. 

5 .7 MODULE AND ACCESSORY WARRANTIES 

The following is a summary of the warranties offered for the TC08 and TC08/N DECtape Controllers. 

5.7.1 Type B, R,W, M, K and A Modules 

All B, R,W, M, K and A modules shown in Catalog C-105, as revised from time to time, are warranted against 
defects in workmanship and material under normal use and service for a period of ten years from date of shipment 
(providing parts are available). DEC will repair or replace any B, R, W, M, K, or A modules found to be de- 
fective in workmanship or material within ten years of shipment for a handling charge of $5.00 or 10% of the 
list price per unit, whichever is higher. Handling charges will be applicable from one year after delivery. 



5-10 



Notwithstanding anything herein contained to the contrary, the Module Warranty outside the continental 
U. S. A. and Canada is limited to repair or replacement of the module, and excludes all costs of shipping, 
customs clearance, or any other related charges. 

5.7.2 System Modules 

All System Modules, Laboratory Modules, High Current Pulse Equipment, G, S, H, Non-Catalog Flip-Chip 
Modules and Accessories are warranted against defects in workmanship and material under normal use and service 
for a period of one year from date of shipment, and DEC will repair or replace any of the above items found to 
be defective in workmanship or materia! during that period. Handling charges will be applicable from one year 
after delivery with the amount of handling charges being available to the purchaser upon request. Notwithstand- 
ing anything herein contained to the contrary, the Module Warranty outside the continental U. S. A. and Canada 
is limited to repair or replacement of the module, and excludes all costs of shipping, customs clearance, or any 

5.7.3 Shipping 

All modules must be returned prepaid to the Digital Equipment Corporation. Transportation charges covering the 
return of the repaired modules shall be paid by the Digital Equipment Corporation except as required by Para- 
graphs 5.7.1 and 5.7.2. The Digital Equipment Corporation will select the carrier, but by so doing will not 
thereby assume any liability in connection with the shipment, nor shall the carrier be in any way construed to 
be the agent of the Digital Equipment Corporation. Please ship all units to: 

Digital Equipment Corporation, 

Module Marketing Services- Repair Division, 

146 Main Street, 

Maynard, Massachusetts 01754 

No modules will be accepted for credit or exchange without the prior written approval of DEC, plus proper 
Return Authorization number. 

5.7.4 Systems 

The TC08 system is warranted against defects in workmanship and material under normal use and service, as 
discussed below, for a period of three (3) months from the date of installation. Notwithstanding the aforesaid, 
in the event that DEC is prevented, by causes beyond its control, from properly installing the equipment, the 
period for this warranty shall be deemed to commence on the thirtieth (30th) day after delivery, or upon installa- 
tion, whichever is sooner. DEC's sole responsibility under this warranty shall be, at its option, to either repair 
or replace any component which fails during this period, provided the purchaser has promptly reported same to 



5-11 



DEC in writing and DEC has, upon inspection, found such components to be defective. The purchaser must ob- 
tain shipping instructions for the return of any item under this warranty provision. Compliance with such instruc- 
tions shall be a condition of this warranty. 

5.7.5 Other Warranty Conditions 

All above warranties are contingent upon proper use in the application for which the products were intended 
and do not cover products which have been modified without DEC's approval, or which have been subjected to 
unusual physical or electrical stress, or on which the original identification marks have been removed or altered, 
These warranties will not apply: 

(1) if adjustment, repair, or parts replacement is required because of accident, neglect, misuse, 
failure of electric power, air conditioning, humidity, control, transportation, or causes other 
than ordinary use, or 

(2) if the equipment is installed by the customer without prior written approval from DEC, or 

(3) if the equipment is removed from its location of initial delivery. 

5.8 SERVICE POLICY 

Unless explicitly agreed upon by the owner and the Digital Equipment Corporation, the responsibility for pre- 
ventive and corrective maintenance, after the warranties have elapsed, lies solely with the owner of the TC08. 
Replacement stockpiles, special tools, test equipment, or other auxiliary equipment listed as a requirement for 
maintenance in this manual, will not be supplied by the Digital Equipment Corporation. 

5.9 SPARE PARTS 

No spares are shipped with the TC08. Table 5-6, however, lists recommended spares, together with minimum 
quantities for maintenance. Check the equipment warranty before ordering a spares replacement. 



Table 5-6 
Recommended TC08, TC08/N Spares 



TC08/N 


TC08 


Number 


Module Type 


Number 


Module Type 


1 




G888 


1 


G888 


1 




Ml 00 


1 


MlOl 


1 




M102 


1 


Ml 03 


2 




MllS 


2 


Mn3 


1 




M121 


1 


M121 


2 




M206 


2 


M206 


1 




M302 


1 


M302 


1 




M633 


1 


M633 



5-12 



r .1 r 1 1 



Because ir is possiDse to repair moauies oy replacing rauiry components^ rour or rne rouowing cnips are recom- 
mended for either controller. 



DEC 7410 N 
DEC 7420 N 
DEC 7430 N 
DEC 74H40 N 
DEC 7474 N 



5-13 



CHAPTER 6 
TC08, TC08/N MODULES 

This chapter provides descriptions of special modules used in the TC08 or TCOS/N controller but not explained 
in the Logic Handbook. Engineering drawings referred to in this chapter appear in Chapter 7. 

6.1 DEC LOGIC 

DEC builds three series of compatible below-ground logic (the B-, R-, and S-series), two series of compatible 
above-ground logic (K- and M-series), an extensive line of modules to interface different types of logic (W- 
series), a line of special purpose modules (G-series), and a line of support hardware for its module line (H- 
series). 

With few exceptions, the DEC below-ground logic operates with logic levels of ground to -0.3V (upper level) 
and -3.2V to -3.9V (lower level), using diode gates which draw input current at ground and supply output 
current at ground. Figure 6-1 shows the voltage spectrum of negative logic systems. 



UPPER LEVEL 
INDETERM 

LOWER LEVEL 



{ 

nant/ '2' 



ov h 

-0.3V 
.3V 
2V 
2V 
9V 



Rgure 6-1 Voltage Spectrum of Negative Logic Systems 

The compatible above-ground logic generally operates with levels of ground to +0.4V (lower level), and +2.0 
to +3.6V (upper level), using TTL or TTL-compatible circuits whose inputs supply current at ground and whose 
outputs sink current at ground . Figure 6-2 shows the voltage spectrum . 



6-1 



UPPER LEVEL- 



INDETERMINANT- 



LOWER LEVEL 



+ 3.6V 

+ 2.4V 
2.0V 

+ 0.8V 
'+0.4V 
OV 



Rgure 6-2 Voltage Spectrum of TTL Logic 



Rnally, a set of special modules designed to operate on the PDP-8 I/O bus are available. Rgure 6-3 indicates 
the voltage spectrum in which they operate. 



UPPER LEVEL 



2.8V - 



INDETERMIN 
LOWER LE 



2.0V 
1.6V 
1.3V 



ant| 

VEL-T 0-8V 
^'"- 1 0.4V 



Rgure 6-3 Voltage Spectrum for Positive PDP-8 l/O Bus Logic 



The DIGITAL Logic Handbook, C-105, is recommended reading for those not already familiar with the basic 
principles of digital logic and the type of circuits used In DEC logic modules. 



6-2 



Timing is measured with the input driven by a gated pulse amplifier of the series under test, and with the output 
loaded with gates of the same series, unless otherwise specified. Percentages are assigned as follows: 0% is 
the initial steady-state level, 100% is the final steady-state level, regardless of the direction of change. 

Input/output delay is the time difference between input change and output change, measured from 50% input 
change to 50% output change. Rise and fall delays for the same module usually are specified separately. 

Risetime and falltime are measured from 10% to 90% of waveform change, either rising or falling. 

6.3 LOADING 

Input loading and output driving are specified in "units", where one unit is 1 .6 mA by definition. The inputs to 
low-speed gates usually draw 1 unit of load. High-speed gates draw 1-1/4 units, or 2 mA. 



6.4 MODULE CHARACTERISTICS 

6.4. 1 G775 Connector Card 

This connector card, designed to plug into a standard H911 slot, is used to terminate the 36-wire flexprint cable 

which interconnects logic signals to the equipment indicator 

panel . All unused inputs should be grounded. Figure 6-4 

shows the logical symbol of the connector card; its circuit 

schematic appears in Chapter 7 as Engineering Drawing 

B-CS-G775-0-1. 



This connector provides isolation for logic levels so that 
these levels can directly drive indicator bulbs in the 
display. 

Input loading is 2 units dynamic and 1 unit static (dc). 

6.4.2 G879 Transports Detector Module (see Figure 6-5) 

This is a series G single-height module designed to detect 
an error condition in the select circuitry of the DECtape 
system. It will switch if the input voltage is too low, indi- 
cating that no transport has been selected, or too high when 
more than one has been selected. The circuit schematic 
appears in Chapter 7 as Engineering Drawing B-CS-G879-0-1 . 



A1 




B1 




CI 




D1 




El 




F1 




HI 




J1 




K1 




L1 




Ml 




N1 




P 1 




R1 




SI 




T1 




U1 




V1 









A2 




B2 




C2 




D2 




E2 




F2 




H2 




J2 




K2 




L2 




M2 




N2 




P2 




R2 




S2 




T2 




U2 




V2 









Figure 6-4 The G775 
Connector Card Logic Symbol 



6-3 



Inputs: Minimum input impedance 100 Q 

Levels OV to -15V 
Outputs: Standard TTL levels 
Fan out - 30 units 



Input/Output: Function 




Input Voltage 


Output Voltage 


-15V -►-9V 


OV 


- 9V - -6V 


+3V 


- 6V - OV 


OV 



V2 



G879 



U2 




Figure 6-5 The G879 Transport Detector Module 



Power Dissipation: 90 mA from -15V 
25 from +5V 

Application: This module was designed to detect when either no transport or more than one transport has been 
selected in a DECtape system. It can be driven by a W040 module in series with a 100 Q resistor as shown in 
Figure 6-6. When either no W040 driver or more than one driver are driving the G879, its output goes nega- 
tive. With only one input, the output stays high (+3V). 

6.4.3 G888 Manchester Reader/Writer Module (see Figure 6-7) 

This is a G-series single-height module with a reader and a writer. The reader is a high-gain amplifier with 

positive feedback which will respond to inputs of 500 |jV. 

There are three stages to the reader; a linear amplifier 

with a gain of 100, a zero crossing detector, and a limiter 

which drives a 7400-series TTL gate. A test point, pin 

M2, is provided to sample the output of the first stage. 



W040 



iooni/4w 




G879 



The writer is a push/pull amplifier which drives current in 
one direction or the other as a function of the relative 
polarity of its inputs. Its inputs feed a 7400-series gate. 

Inputs: WRITER 

Standard TTL voltage 

Load at OV is 1 unit 

R2 should be tied to +3V when not used . 

READER 

It can detect an input voltage as low as 500 pV. 



W040 



I00ni/4W 



Figure 6-6 G879 Application 





Figure 6-7 The G888 Reader/Writer 



6-4 



Oi ..!._. ,jL- . \A/DTTCD 

The writer can drive 100 mA In either direction. Pins L2 and M2 are the outputs of the 7400 TTL 
gates. Pins J2 and K2 are the outputs which drive the tape head. 

READER 

Outputs U/ V are standard TTL voltages. 

Fan Out U2 9 units 
V2 10 units 

Pin H2 is a test point which monitors the output of the first stage. 

Standard TTL levels. 

Power Dissipation: 50 mW at +5V, 250 mW at -15V. The circuit schematic of the reader/writer appears in 
Chapter 7 as Engineering Drawing B-CS-G888-0-1 . 

Application: This module is used to drive or receive current to or from the DECtape heads of the TU55 or TU56 
transports . 

6.4.4 MlOO Bus Data Interface 

The MlOO is a single-height module which contains fifteen two-input NAND gates arranged for convenient 
data strobing off the PDP-8 or PDP-8/L negative l/O bus. One input of each gate is tied to a common line so 
that all data signals on the second input of each gate will be enabled simultaneously. The circuit schematic 
appears in Chapter 7 as Engineering Drawing C-CS-MlOO-0-1 . 

Inputs: Minimum input impedance 5K 

Standard negative l/O Bus voltages 
Input load at CI - 15 units 

Outputs: Fan Out - 10 units 

Input/Output Delay 40 ns typically 
Standard TTL levels 

Power Dissipation: 10 mA maximum at -15V 
60 mA maximum at +5V 

Application: The MlOO is used to accept data off negative logic PDP-8 buses. It is pin-compatible with the 
positive logic MlOl . The enabling line CI cannot be used as a strobe line because the output signals are in- 
determinate for 200 ns after the enabling line becomes true. A data input of -3V will yield an output of ground 
when CI is gated by a positive voltage level . (See Figure 6-8 for logic diagram.) 



6-5 






> 






-ry- 





B 1 



El 



H 1 



K 1 



■^y 



Ml 



t^ 





SI 



U1 



H2 



K2 



M2 



P2 



S2 



U2 









H> 



-t> 



POWER 

-A2 +5V 

— C2, T1-GND 

— B2 15V 



r> 








F2 



J2 



L2 



N2 



R2 



T2 



V2 



Figure 6-8 The Ml 00 Bus Data Interface Module, Logic Diagram 



6-6 



6.4.5 Ml 02 Device Selector (for use with negative voltage bus) 



OPTION SELECT 





LI 



-^M 



P2 



R2 



lOPl 



U^ 



I0P2 ^^ 



S2 



I0P4 y^ 




N 1 






\Tyr<^ 



\^I>^^^ 



A1 



B 1 



C 1 



E 1 
F 1 



POWER 



-• A2 +5V 

-• C2,T1 — GRD 

+ 3 — VI — *L0G!C1 
-ii B2 15V 



Figure 6-9 The Ml 02 Device Selector 



The M102 (see Figure 6-9) is used to decode the six device address bits transmitted in complementary pairs on 
the negative bus of the PDP-8, PDP-8/l. The outputs of the M102 are compatible with M Series TTL logic. The 
M102 is pin-compatible with the M103 Positive bus device selector, with the exception of the address inputs. 
The true states of the BMB outputs of the PDP-8 and PDP-8/l are defined as ground where the true states of the 
PDP-8/l positive bus and PDP-8/L are defined as an active voltage state. Because of this the complement of 
the address bits used for an Ml 03 must be connected to the Ml 02. 

Because the address complement is tied to the pins D2, E2, F2, H2, J2, K2, an M103 may be directly sub- 
stituted for an M102 when changing from a negative to a positive bus. The circuit schematic of the M102 appears 
in Chapter 7 as Engineering Drawing C-CS-M 102-0-1 . 

Inputs: U2 represents 1 .25 TTL unit loads, Jl , Ml represents 1 TTL PI , Rl , SI , Ul , M2, and T2 standard levels 

of -3 volt and ground. Input load is 1 mA, shared among the inputs that are at ground. 

P2, R2, S2, HI and LI 
0.2 mA when Vin =0V 



6-7 



0.0 mA when V in = -3V 
Propagation Delay 40 ns typ 

Outputs: Kl and Ml can drive 10 TTL unit loads. Al , Bl , CI , Dl , El , Fl can each drive 37 TTL unit 
loads. U2 can drive 16 TTL unit loads. 

Conversion: Logic Diagram 

An active voltage is a True State, i .e. , -3V or +3V = "1" 
A ground is a True State 

Power: +5 V at 1 30 mA . (maximum). 
-15 Vat 40mA. (maximum). 

6.4.6 M228 Mark Track Decoder 

The M228 mark track decoder is a double-height M-series board designed specifically for the TC08, TC15 
DECtape controller. It contains a 9-bit shift register W1-W9, a six-bit state generator, decoding, and control 
logic. Its operation is explained in detail in Chapter 3 of this manual . The circuit schematic appears in 
Chapter 7 as Engineering Drawing D-CS-M228-0-1 . 



Inputs: Standard TTL Voltages 






Loading 


AV2 






26 


BH2 






18 


AS2, BD2, AN2, BR2 






1 


BCl 






12 


AR2, BSl, BK2, BL2, BR' 


1 




1 


ANl 






1 


Outputs: Standard TTL Voltages 






Fan Out 


BJ2, BE2, BV2 






7 


BF2, AK2 






8 


ALl, AKl, AM2 






5 


AMI 






10 


AUl 






9 


API, AH2, BM2, AJl, 


AU2, 


, BUI 


8 


AD2, BT2, BU2 






8 


AJ2, AT2 






6 


AF2, BN2, AHl, BP2, 


BUI, 


AE2, BS2 


10 



6-8 



Power Dissipation: 955 mW at 5V 

Application: This module has been designed specifically to perform the mark track decode and state generator 
functions of the TC08 and TC15 DECtape controller. 

6.4.7 W032 Connector 

This single-height connector board is intended to be used with 5 cables of 3 conductor shielded coaxial cable. 
It has no elements. The circuit schematic appears in Chapter 7 as Engineering Drawing B-CS-W032-0-1 . 

6.4.8 716 Indicator Supply 

This power supply delivers 6.5 Vdc and 9 Vac to the indicator panel of the TC08 or TC15 DECtape system. The 
circuit schematic appears in Chapter 7 as Engineering Drawing B-CS-716-0-1 . 

Inputs: 115 Vac 50/60 Hz 

Outputs: 6.5 Vdc at 4.5A 

9 Vac at 100 mA (This Is a halfwave rectified signal.) 

Power Dissipation: 80W maximum 

6.4.9 M623 Bus Driver (see Figure 6-10) 

The M623 contains twelve two-input AND gate bus drivers for convenient driving of the positive input bus of 
either the PDP— 8/ I or PDP— 8/L. Each driver can sink 100 mA at "round '^nd "^llows "^ maxim.um outi^ut volt'^'^^ 
of +20V. The output consists of an open collector NPN transistor. The circuit schematic appears in Chapter 7 
as Engineering Drawing C-CS-M623-0-1 . 

Inputs: Input levels are standard TTL levels of OV and +2.4V. Data inputs Al , Bl , Fl , HI , Ml , Nl , D2, E2, 
K2, L2, R2, and S2 each present one TTL unit load. All other inputs present two unit loads. 

Outputs: A driver output will be at ground when both inputs are at ground. Output rise and fall times of TTL 
are typically 30 ns when a 100 mA resistive load is connected to a driver output. Output voltage 
must not exceed +20V. 

Power: +5V, 71 mA (maximum) plus external load. 

.* A2 +5V 



C2, Tl 
Ul, VI 



6-9 



GRD 



Al 
C I 



Fl 



H 1 



Ml 



N1 



J1 f— O 



PI f C 




^-d \ 

s — cLJ" 



D1 



E 1 





K 1 



L 1 





R 1 



S 1 



D2 



F2 •— 



E2 



K2 
M2 



L2 



R2 



T2 



S2 



o 



T> 



f—0 



H2 



J2 





N2 



P2 



"Jc^u, 




V2 



Rgure 6-10 M623 Driver 

6.4.10 M633 Negative Bus Driver (see Figure 6-11) 

The M633 conf-ains twelve bus drivers intended for convenient driving of the negative bus of the PDP-8, PDP-8/l, 
Each driver consists of an open collector PNP transistor. It is pin-compatible with the M623 positive voltage 
bus driver. The circuit schematic appears in Chapter 7 as Engineering Drawing C-CS-M633-0-1 . 

Inputs: Input levels are standard TTL levels. Data inputs Al , Bl , Fl , HI , Ml , Nl , D2, E2, K2, L2, R2, and 
S2 each present one TTL unit load. All other inputs represent two unit loads. 

Outputs: Open collector PNP transistor capable of supplying 20 mA from ground. Voltage applied to the out- 
put should not exceed -6V. 

Conversion: Logic Diagram: An active voltage is a True State; i.e., -3V or +3V = "1 " . 

A ground is a True State. 
Grounded inputs will yield grounded outputs. 



6-10 



Propagation Delay: 4U ns lyp 

Power: +5V at 100 mA (maximum) 
-15V at 40 mA (maximum) 



c 1 



Bl 



X>4>-" 






V^ 



E 1 



D2 
F2 



E2 



t— o 







l^ 



H2 



J2 



F 1 



J 1 



H 1 



A 



vA^^r^^^ 




L 1 



K2 
M2 



L2 



A r\ 



rA.^r^y^ 



T>^>- 



N2 



P2 



N1 






~n^ 



R 1 



S 1 



R2 



S2 



POWER 

- A2 +5V 

- C2,T1 — GND 

- B2 !5V 



>^- 



Figure 6-11 M633 Negative Bus Driver 




U2 



V2 



6-11 



CHAPTER 7 
DOCUMENTATION 

This chapter contains al! of the engineering drawings applicable to this equipment. Table 7-1 lists the signal 
mnemonics, the full names of the signals, and the prints on which each can be found. The print number in the 
right-hand column of this table refers to the final digit of the TC08 series of prints; e.g. , print 11 would refer 
to engineering drawing D-BS-TCOS-O-ll. 

These drawings are listed in Table 7-2 by number and title, together with the page in this volume on which each 
can be found. Because DEC is constantly improving its products, it is possible that several engineering changes 
might have occurred in the TC08 controller since these drawings were "published. !n case of discref^ancies be- 
tween the drawings contained in this chapter and those received with the controller, the set of prints which came 
with the equipment should be used for reference. 



Table 7-1 
TC08, TC08/N Signals 



Signal Mnemonic 


Signal Name 


TC08 Print 


OTO AC 


Clear the Accumulator 


1, n 


TO DTB 


Clear the DECtape Buffer 


4,5,8 


OTOEF 


Clear the Error Flags 


6 


TO LPB 


Clear the Longitudinal 
Parity Buffer 


9 


TO STA 


Clear the Status A Register 


2 


TO STATE 


Clear the State Generator 


3,7 


OTO W 


Clear the Window Register 


3,7 


1 TODF 


Set the Data Flag 


4 


1 TO DTP 


Set the DECtape Flag 


4,6 


ADDR ACC 


Address Accepted 


1,4, 11 


B -BRK 


Break State 


1 


B - RUN (0) 


Computer Not Running 


2 


B - RUN (1) 


Computer is Running 


1,2 



7-1 



Table 7-1 (Gont) 
TG08, TG08/N Signals 



Signal Mnemonic 


Signal Name 


TG08 Print 


B - XSTA 


XOR Stafus Register A 
Buffered 


1.4,6 


BAG 00 
BAG n 


Buffered Accumulator on 


1,2,4, 10, 11 


BLK IN SYNG 


Block in Synchronization 


1,4 


BMB 00 (0) - 
BMBll (1) 


Buffered Memory Buffer 


8, 10, 11 


BMB TO DTB 


Transfer Memory Buffer 
to the DEGtape Buffer 


1,8 


C00{0), (1) 


Gounter 


4,5,9, 12 


COl (0), (1) 


Gounter 1 


4,5, 9, 12 


GKOO(O), (1) 


Glock Gounter 1 


3, 10 


CKOl (0), (1) 


Glock Gounter 2 


3 


GLRDF 


Glear Data Flag 


4 


GLRDTF 


Glear DEGtape Flag 


4 


GOMP+ SH 


Gomplement or Shift 


5, 8 


GSTA 


Glear Status Register A 


1,2,6 


DATAO, 1 


Data State 


4,5,7, 12 


DBOO (0) - 
DBll (0) 


Data Bits 


11, 12 


DF(0) 


Data Flag on a Zero 


4,5, 11 


DF(1) 


Data Flag on a One 


4,6, 12 


DTB 00(0) - 
DTB 11 (1) 


Data Buffer 0-11 


8, 9, 11, 12 


DTP (0) 


DEGtape Flag on a Zero 


1,4,5, 11 


DTP (1) 


DEGtape Flag on a One 


4,6, 12 


DTSF 


Skip on DEGtape or Error 
Flags 


1 


EAOO 


Extended Address Bit 


11, 12 


EAOl 


Extended Address Bit 1 


11, 12 


EA02 


Extended Address Bit 2 


11, 12 


EP(0) 


Error Flag on a 


1,6, n 


EF(1) 


Error Flag on a 1 


6, 12 


END (0), (1) 


End of Tape Error 


6, 11, 12 


ENI(0),(1) 


Enable Interrupt 


1,2, 11, 12 



7-2 



iQDie /-I (vwonr; 
TC08, TC08/N Signals 



Signal Mnemonic 



Signal Name 



TC08 Print 



FROO(O) 

FROO(l) 

FRO! (0) 

FRO] (1) 

FR02 (0) 

FR02 (1) 

FR03 (0) 

FR03 (1) 

I/0+ 1 TOCAINH 

I/O TO AC 

I/O ADDR ACC (0) 

I/O B-BRK (0) 

I/O B - RUN (1) 

I/O BAG 00 (1) - 
V w D/-\»^ I ' ( I ; 

I/O BMB 00 (1) - 
I/O BMB n (1) 

I/O BRK RQ 

I/O BWCO 

I/O DATA IN 
I/O INT RQ 
I/O PWR CLR 
I/O SKP RQ 
I/O TS03 
I/O TS04 
IMOO- IMll 
INTRQ 



Function Register 
Bit on a 

Function Register 
Bit on a 1 

Function Register 
Bit 1 on a 

Function Register 
d:i 1 1 

Function Register 
Bit 2 on a 

Function Register 
Bit 2 on a 1 

Function Register 
Bit 3 on a 

Function Register 
Bit 3 on a ] 

Inhibit Incrementing the 
CA 

Clear the Accumulator 

Address Accepted 

Break 

Computer Running 

Buffered Accumulator 

Buffered Memory Buffer 

Break Request 

Buffered Word Count 
Overflow 

Data In 

Interrupt Request 

Power Clear 

Skip Request 

Time State 3 

Time State 4 

Input Mixers 

Interrupt Request 



4, II 
4, 12 

5, n 

2, 5, 6, n, 12 

11 

12 

n 

12 
, 12 

, 12 

r 12 

12 

, 12 

n, 12 

, 12 
, 12 

, 12 

, 12 

12 

, 12 



, 12 
11 



7-3 



Table 7-1 (Cont) 
TC08, TC08/N Signals 



Signal Mnemonic 


Signal Name 


TC08 Print 


lOP 1 


Input/Output Pulse 1 


1, 12 


IOP2 


Input/Oufput Pulse 2 


1, 12 


IOP4 


Input/Output Pulse 4 


1, 12 


LDMF 


Load Status Register B 


1 


LPB 00 (0) - 
LPB 05 (1) 


Longitudinal Parity Buffer 


8,9, 12 


LPB NOT EQ 1 


Longitudinal Parity Buffer 
is not Equal to 1 


6,9 


LPBTODTB 


Transfer Contents of LPB 
to the DTB Register 


8,9 


M - STOP 


Stop the Transport 


2,3 


MCOO(O), (1) 


Mark Track Counter Bit 


4,5,6, 12 


MCOl (0), (1) 


Mark Track Counter Bit 4 


4,5,6, 12 


MC02 (0), (1) 


Mark Track Counter Bit 2 


4,5,9, 12 


MFOO(O), (1) 


Memory Field Bit 


1, 11, 12 


MFOl (0), (1) 


Memory Field Bit 1 


1, 11, 12 


MF02(0), (1) 


Memory Field Bit 2 


1, 11, 12 


MK BLK END 


Mark Block End 


6,7,9 


MK BLK MK 


Mark Block Mark 


4,7 


MK BLK START 


Mark Block Start 


6,7 


MK BLK SYNC 


Mark Block Sync 


7 


MK DATA 


Mark Data 


6,7 


MK DATA SYNC 


Mark Data Sync 


7 


MK END 


Mark End 


6,7 


MKT(0),(1) 


Mark Track Counter 


2,4,5,9, 12 


MKTK (0), (1) 


Mark Track Head 


6, 11, 12 


MOVE 


Move 


2,6 


MR 00(0), (1) - 
MR 01 (0), (1) 


Motion Register 0, 1 


2, n, 12 

2,3, 11, 12 


PAR(O), (1) 


Parity Error Flag 


6, 11 


PC + ES 


Power Clear or Error Stop 


2,6 


PWR CLR 


Power Clear 


1,2,4,5,6 


RD + WD 


Read or Write Data 


2,4,6 


RD EN 


Read Enable 


4 



7-4 



■ S^t-^ IN^ / ■ \\^\Jl It / 

TC08, TC08/N Signals 



Signal Mnemonic 


Signal Name 


TC08 Print 


RD EN LPB 00-02 


Read Enable Longifudinal 
Parity Buffer Bits 0-2 


9 


RD EN LPB 03-05 


Read Enable Longitudinal 
Parity Buffer Bits 3-5 


9 


RDD 00 - RDD 02 


Read Data Tracks 0-2 


8,9, 10 


RDMK (0), (1) 


Read Mark Track Head 


7, 10 


READ ALL 


Read All Mode 


2.4 


READ DATA 


Read Data Mode 


2,4,6 


RSTA 


Read Status Register A 


1, n 


RSTB 


Read Status Register B 


1, n 


SE 




2,6 


SEARCH 


Search Mode 


2,4, 11 


SEL(O), (1) 


Select Error 


6, n, 12 


SHDTB 


Shift the Data Buffer 


5, 6, 8 


SH EN 


Shift Enable 


5, 8 


SH ST 


Shift the State Generator 


1, 7 


SH ST - B 


Shift the State Generator 
Buffer 


1,7 


SHIFT CK 


Shift Checksum State 


5r7 


SKPRQ 


Skip Request 


1, 11 


SPDY 


Speed Delay 


3 


STBLKMK (0), (1) 


Block Mark State 


5,6,7, 12 


STCK(O), (1) 


Checksum State 


4,5,6,7, 12 


ST CK P 


Checksum State Pulse 


4 


ST DATA 


Data State 


5 


ST FINAL (0), (1) 


Final State 


4,5,7,9, 12 


STIDLE(0),(1) 


Idle State 


5,6,7,9, 12 


ST REV CK 


Reverse Checksum State 


4,5,7, 12 


SWTM 


Write Timing & Mark Track 
Switch 


3, 5, 6, 12 


SYNC 


Synchronize 


4,7 


SYNC - P 


Sync Pulse 


4 


SYNC EN 


Enable Synchronization 


7 


TOO 


Transport 


2, 12 



7-5 



Table 7-1 (Cont) 
TC08, TC08/N Signals 



Signal Mnemonic 


Signal Name 


TC08 Print 


TO! 


Transport 1 


2, 12 


T02 


Transport- 2 


2, 12 


T03 


Transport 3 


2, 12 


T04 


Transport 4 


2, 12 


105 


Transport 5 


2, 12 


T06 


Transport 6 


2, 12 


T07 


Transport 7 


2, 12 


TFWD 


Move Transport Forward 


2, 12 


T GO 


Start the Transport 


2, 12 


T PWR CLR 


Transport Power Clear 


2, 12 


TREV 


Transport Move Reverse 


2, 12 


T SINGLE UNIT 


Transport Single Unit 


6, 12 


TSTOP 


Stop the Transport 


2, 12 


TTRK(O), (1) 


Timing Track Head 


3, 10 


T WRITE OK 


Transport Write OK Switch 


2, 12 


TIM(0),{1) 


Timing Error 


6, 11, 12 


TMEN 


Enable Write Timing & 
Mark 


3, 10 


TPOO 


Timing Pulse 


3,4,5,6,7 


TPOO A 


Timing Pulse Delayed 


3,5,9 


TPOl 


Timing Pulse 1 


3,4,5,7,9 


TPOIA 


Timing Pulse 1 Delayed 


3,4,9 


TS03 


PDP-8 Timing Pulse 3 


1, n 


U+MDY 


Unit or Motion Delay 


3 


USR 00 - USR 02 


Unit Select Register 


2, 11, 12 


UTS (0) 


Up to Speed Reset 


3 


UTS (1) 


Up to Speed Set 


3, 5, 12 


W+ UTS 


Write Enable or Up to 
Speed 


3 


W-INH(O), (1) 


Write Inhibit 


4,5 


WOl(l) - W09(l) 


Window Register Bits 1-9 


7, 12 


WBOO - WB02 


Write Buffer 


8, 9, 10, 12 


WC{0), 0) 


Word Count Overflow 


1,4,5, 12 


wco 


Word Count Overflow Pulse 


1 



7-6 



TC08, TC08/N Signals 



Signal Mnemonic 


Signal Name 


TC08 Print 


WREN(O), (1) 


Write Enable 


3,5,9, 10, 


12 


WRITE ALL 


Write All Mode 


2,4,5 




WRITE DATA 


Write Data Mode 


2,4,5 




WRITE OK 


Write OK 


2,5,6 




WRITE OK + UTS 


Write OK or Up to Speed 


5 




WRTM 


Write Timing and Mark 
Track 


2,3,5,6 




WRTM + FR03 


Write Timing and Mark or 
Function Register ^Z 


2,4 




XOR TO LPB 


Exclusive OR Contents to 
the Longitudinal Parity 
Buffer 


9 




XSADY 


XOR Status A Time Delayed 


2,6 




XSAD 


XOR Status A Pulse Delayed 


1,6 




XSTA 


Exclusive OR Status A 
Register 


1, 2, 3, 6 




XTDY 


Cross Talk Delay 


3 





Table 7-2 
Engineering Drawings 



Drawing No. 


Title 


Page 


A-ML-TC08-0 


Master Drawing List, DECtape Control 


7-9 


A-PL-TC08-0-0 


DECtape Control 


7-10 


A- PL -7006394-0-0 


Wired Assembly TC08 


7-11 


A-SP-TC08-0-16 


Check-out Procedure (4 Sheets) 


7-12 


B-CS-G775-0-1 


Connector Card Indicator Panel G775 


7-16 


B-CS-G879-0-1 


Transport Detector G879 


7-17 


B-CS-G888-0-1 


Manchester Reader/Writer G888 


7-18 


B-CS-W032-0-1 


Connector W032 


7-19 


B-CS-716-B-1 


Circuit Schematic 716B 


7-20 


C-CS-MlOO-0-1 


Bus Data Interface MlOO 


7-21 


C-CS-M102-0-1 


Device Selector Ml 02 


7-22 


C-CS-M623-0-1 


Bus Driver M623 


7-23 


C-CS-M633-0-1 


Negative Bus Driver M633 


7-24 



1-1 



Table 7-2 (Cont) 
Engineering Drawings 



Drawing No. 


Title 


Page 


D-CS-M228-0-1 


Mark Track Decoder M228 


7-25 


D-UA-TC08-0-0 


DECtape Control 


7-27 


D-BS-TC08-0-1 


I/O Control 


7-29 


D-BS-TC08-0-2 


Status A 


7-31 


D-BS-TC08-0-3 


TP Generator 


7-33 


D-BS-TC08-0-4 


Flags 


7-35 


D-BS-TC08-0-5 


Control 


7-37 


D-BS-TC08-0-6 


Errors 


7-39 


D-BS-TC08-0-7 


Mark Track Decode 


7-41 


D-BS-TC08-0-8 


DTB/WB 


7-43 


D-BS-TC08-0-9 


LPB 


7-45 


D-BS-TC08-0-10 


I/O Bus Invts/Ind Dvrs 


7-47 


D-BS-TC08-0-n 


I/O Bus Drive Receive 


7-49 


D-BS-TC08-0-12 


I/O Bus Connectors 


7-51 


D -AD -7006394-0-0 


Wined Assembly TC08 


7-53 


D-DI-TC08-0-15 


DECtape Control 


7-55 


D-TD-TC08-0-17 


TC08 Timing 


7-^1 


K-MU-TC08-0-13 


Module Utilization List 


7-59 


K-PL-TC08-0-13 


Module Utilization List 


7-59 


K-WL-TC08-0-14 


Wire List TC08 


7-60 



7-8 



o 
■5 • 

It 



O M 

c s 
1^ 



o .s 



MASTER DRAWING LIST 



DWG. NC. 



REV 
LET. 



NO. OF 
ISHEETS 



TITLE 



D-uA-Tcef8-ef-ef 



A 



DECTAPE CONTROL 



A-PL-TC0b-0-0 



DECTAPE COINITROL. 



D-BS-TC08-0-1 



I/O CONTROL 



D-BS-TC08-0-2 



STATUS "A" 



* »- ± 
j: o o 

i=- 

8.1° 

e o • 

►- • E 



D-BS-TC)2f8-gf-3 



TP GEN 



D-BS-TCi2f8-0-4 



B 



FLAGS 



D-BS-TCef8-0-5 



CONTROL 



D-BS-TC08-0-6 



B 



ERRORS 



D-BS-TCiZf8-gf-7 



MARK TRACK DECODE 



D-BS-TCgfS-ef-S 



A 



DTB/WB 



D-BS-TC08-0-9 



B 



LPB 



D-BS-TCe(8-ef-10 



I/O BIS INVTS/IND DVRS 



D-BS-TCi2f8-i2f-ll 



I/O BUS DRIVE/RECETVE 



P-IC-TC08-0-12 



I/O BUS CONNECTORS 



K-^ MU ^TC08-0-13 



MODULE UTILIZATION LIST 



K-WL-TC08-0-14 



WIRE LIST TC08 



U-AJJ- /U06 J^^-J^-ii3 



WIkejj ASS'Y tC08 



A-PL-7006394-ef-ef 



A 



WIRED ASS'Y TCef8 



D-DI-TC08-ef-15 



B 



DECTAPE CONTROL 



CHECK-OUT PROCEDURE 



A-SP-TC08-0-16 



A 



D-TD-TC08-0-17 



TC08 TIMING 



D-IC-TC08-0-18 



A 



AC POWER WIRING 



D-IC-TC08-0-19 



DC POWER WIRING 



D-IC-TCO8-0-20 



CABLE CONFIGURATION 



■n _ 7\ T5 —mr" rvQ _ A _ o 1 



r'7\T3T'\TTrn TAVrvTTTl 
• — ■ ■ ■ -.^ jLj X ±jjn. J. v-? w X 



REVISIONS 



REV. 



A 



E 
F 
H 



DATE 




00001 
QQ002 

Mm 



CHG. NO. 



APP'D. 

D.L. 

D.L. 



L 



DRN. 

IG.GIANOULI 



aS/X' 



f^--^ / 



PROJ.ENG. 



PRODv 



DATE 



6/ 

13/6' 



DATE 



DATE 



M^ 



da;pe 

■L 



DATE 

1hi. 



FIRST USED OH 



SCALE 



SHEET 



OF 




EQUIPMENT 
CORPORATION 

MAYNARD. MASSACHUSETTS 



TITLE 



DECTAPE CONTROL 
60 HZ 



SIZE 



CODE 

ML 



DIST. 



NUMBER 

TC08-0 



REV. 

H 



)EC FORM NO. 
>RA 103 



7-9 



I 





DIGITAL EQUIPMENT CORPORATION 




QUANTITY/ VARIATION 


MAYNARD , MASSACHUSETTS 

PARTS LIST 


o 

O 
1 

CO 

la 
u 

EH 


o 

in 
< 

1 

00 

u 






















MADE BY G. MARINI 
DATE 6723/69. 


CHECKED R. COOK 
DATE .. 7/24/69 


SECTION 


ENG ^ y^.^xr i /ry 
DATE "^'J /-y"^ 


PROD ^-(ajc^*\^ 
DATE <={ h l&^^ 


tSSUED SECT. 


ITEM 
NO. 


DWG NO. /PART NO. 


DESCRIPTION 


1 


D-AD- 7006331-5-0 


INDICATOR PANEL ASSY fTClZJ8) 


1 


1 






















2 


D-AD-7006394-0-0 


WIRED ASSY fTCe(8) 


1 


1 






















3 


1202279 


SWITCH. TOGGLE 


X 


X 






















4 


A-DC-5308493-0-0 


DECALS (TC08) 


1 


1 






















5 


9107450-00 


WIRE #24 AWG STRD TEF INS BLK 


A/I A/I 






















6 


9107450-44 


WIRE # 2"* AWG STRD TEF INS YEL 


A/I A/I 






















7 


D-UA-BCefRC-C^-Pf 


CABLE. DUAL MYLAR M9ef3- f 2) W(2f31 


5 


5 






















* 


D-UA-832-F-0 


POWER CONTROL 832 -F 


1 
























* 


D-UA-832-E-0 


POWER CONTROT. R3P-E 




1 






















* 


D-UA-783-0-1 


783 POWER SUPPLY 


1 
























* 


n-TTA-7R^A-n-l 


pnwRR fiTTppT.Y TYPE 78 3A 




1 






















* 


E-AD-7005474-0-0 


FAN ASSY 


1 


1 






















* 


D-AD-7005909-0-0 


AC DIST PANEL 


1 


1 






















•V 


7005128 


POWER CORD 25' 


1 


1 






















* 


1209340-1 


Mat-N-LOC CONN 


1 


1 






















* 


1209378-1 


PIN, CONTACT 


8 


8 












































































































































































* 


NOT SHOWN ON ASSY 




























TITLE 

DECTAPE CONTROL 


ASSY NO. 

D-UA-TC08-0-0 


SIZE CODE 

A PL 


NUMBER 

TC08-0-0 


REV. 

A 


ECO NO. 

TC08- 
00003 










SHEET 1 OF 1 


°'^'- 6-1 1 1 1 1 1 1 1 1 1 



DEC FORM NO. 
DRA 110 



I 





DIGITAL EQUIPMENT CORPORATION 




QUANTITY/VARIATION 


MAYNARD , MASSACHUSETTS 

PARTS LIST 


























MADE BY G. GIANOULIS 
DATE 6/12/69 


CHECKED <r^ (S^^r^CtP. 
DATE (^/tL7/C? 


SECTION 

1 


ENG /.: ^:^^.-:-^'^::'f 
DATE^ ■S''/. 7 


PROD ._ / p / 

DATE 1 Jo..A— ^^ f/^(Ci 


ISSUED SECT. 

1 


ITEM 
NO. 


DWG NO. /PART NO. 


DESCRIPTION 


1 


1205541 


BUS STRIP 


\/R 
























2 


9107560-1 


2 2 AWG BUS WIRE 


\/R 
























3 


9107265-09 


#22 TUBING, TEFLON, WHITE 


\/R 
























4 


9105740-44 


30 AWG SOLID TEF INS. WIRE, YELLOW 


\/r 
























5 


9105740-66 


30 AWG SOLID TEF INS. WIRE, BLUE 


\/R 
























6 


A-DC-7406371-0-0 


LOGIC FRAME DECALS 


\/R 
























7 


D-AD-5404491-0-0 


H911 MTG PANEL 


2 






















































REF 


K-WL-TC08-0-14 


WIRE LIST TC08 


1 






























































































































































































































































































































































































































TITLE 


ASSY NO. 

D-AD-7006394-0-0 


SIZE ( 

A 


:ODE 

PL 


NUMBER 
7006394-0-0 


REV. 

A 


ECO NO. 

TC08 
00005 










SHEET 1 OF 1 


DIST. 1 1 



DEC FORM NO. 
DRA 110A 



b ^ ~ 

a) o i_ 
Q. ^ o 

0) S i 
!;; o. TO 

2 E 



™ ^ ^, 

"O 1- <D 0) 

c o a CL 

™ o •- S 

TO 0) a) 



DIGITAL EQUIPMENT CORPORATION 

MAYNARD, MASSACHUSETTS 



DATE 9-29-69 



TITLE TC08 & TC08N CHECKOUT PROCEDURES 



REVISIONS 



REV 



DESCRIPTION 



CHG NO 



ORIG 



DATE 



APPD BY 



t^ ' - 1 



DATE 



(- u 



A 



TC08- 
0000s 



LAZUKA 



3-n-7C 



y-f ¥-70 



A. EQUIPMENT REQUIREMENTS 

1. TC08 Back Panel 

2. TC08 Indicator System 

3. TC08 or TC08N Module Kit 

4. TC08 and TC08N Logic Prints 

5. Set of TCOl Maindec's 

5. 783 Power Supply or Equivalent 

7. 715 Indicator Supply 

8. Minimum of 1 TU55 or TU56 Transport 

9. Dual Trace Scope 

B. PRELIMINARY CHECKS 

1. With all other modules removed, plug in the G821 power 
regulator and connect the power OK indicator across pins 
B01M2 and B0'lM2 . 

2. Inspect panel for discrepancies such as power bus shorts, 
broken module blocks, broken wires, bent or pushed in pins, 
and correct installation of the WRTM - normal switch. 

3. By using a Mate-N-Lok connector, connect power to the 
regulator and apply power to the empty panel and check power 
bus for correct voltage. 

4. Connect the 715 power supply to the indicator system and install 
cables. Power up the empty logic panel and the indicator 
system. All indicators except those that are deliberately 

tied to ground should be ON. 

C. PRELIMINARY CHECKS AND SETUP 

1. Plug in all modules and cables. 

2. Test power clear for correct operation. 



ENG 



D . Lazuka 



APPD 



SIZE 

A 



CODE 

SP 



NUMBER 

TC08-0-15 



REV 
A 



DF.C FORM NO. 
DRA 107A 



SHEET .1. 



OF 



7-12 



CONTINUATION SHEET 



TITLE 



TC08 & TC08N CHECKOUT PROCEDURE 



in ths follov/iri'^ inst3riictions? 



FiNEUMOHIC 

LAS 

AND M\l) 

TAD (676i2f) 

DCA 

TAD (i2f4i2f0) 

HLT 

JMP START 

HLT I/O SKIP 



LOCATION 


CODE 


0i2f^j2f 


1604 


jZ^JZfjZfl 


0010 


J2^j2f02 


ijzrii 


<6M'i 


3005 


0004 


Ii2fl2 


M0S 


1402 


0006 


5000 


riridi 




V)Y>Y) 1 


I'^y}^ 


0010 


0011 


)2f^ll 


6160 


^i2fl2 


0400 


This progr 


am wil 


lOPS 1, 2, 


or 4 



nder control of A.C switch bits 8—11. 



The lOT decoding should not be tested. 3y watching the 
outputs of the lOT decoders with a scope and placing the lOP 
in the switch register. 

Place 0004 in the switch and set the XSA DY to the value 
noted on the prints. 

Key in the following program: 



tart 0000 


7604 


LAS 


0001 


7040 


CMA 


0002 


3015 


DCA 


0002 


2014 


ISZ 


0004 


5003 


JMP .-1 


0005 


Z^L-D 


ISZ 


0006 


5003 


JMP .-3 


0001 


1013 


TAD 


0010 


6764 


DTXA 


0011 


5000 


JMP (START) 


0012 


7402 


HLT I/O SKIP 


0013 


0400 




0014 


0000 




0015 


0000 





This program causes the direction bit to X ORed at a rate 
determined by the contents of the switch register. This 
program generates U&M and also fires the U&M DY which should 
nciw be set to the value noted on the prints. 



D . Lazuka 



SIZE 

A 



CODE 

SP 



NUMBER 

TC08-0-16 



REV 

A 



DEC FORM NO 
DRA 108A 



SHEET 



OF 



7-13 



CONTINUATION SHEET 



TITLE TC08 & TC08N CHECKOUT PROCEDURE 



By removing the G888 in slot Al8 and adding a temporary 
jumper between d14k2 and Dl4Ul, and also changing address 13 
of the previous program to ALL ZERO's!! The program may be 
used to fire the SP DY v^h ich should now be set to the value 
noted on the prints. After the SP DY is set, remove the 
jumper, insert the G888 back into slot Al8, and replace the 
original contents of address 13 (0400) . 

By adding the following instructions to the previous program, 
a tape rocking program can be produced. Start program at 
location 16. 



0016 1600 

0011 1^23 

0020 6766 

^iZf 21 5000 

i2fi2f22 74^2 

0023 0200 



CLA 

TAD 

DTLA 

JMP START 

HLT I/O SKIP 



9. By using the following program the write timing and mark 
track clock may be enabled: 

Start 6600 1004 TAD 

0001 6766 DTLA 

iS002 6764 DTXA 

0003 5002 JKP .-1 

0004 0260 

Place unit 8 on-line and write enabled. Place WRTM normal 
switch in the WRTM position. Start the program. The clock 
should be set to the valve noted on the prints. 

D. BASIC TESTING 

1. The TCOl basic exerciser (Maindec-08-D3BB-D) provides a 
comprehensive test procedure. The tests also follow' in a 
logical sequence of testing. If this sequence is followed, 
checkout time and problems will be held to a minimum. 

2. After all tests of the basic exerciser have been run 
correctly, the DECtape formatter (DEC-08-EUFA-D) should be 
run . 

3. DECtrex 1 (Maindec-08-D3RA-D) should be made to run error 
free. 

4. The DECtape Library System (DEC-08-SUAl-LA) should now be 
tried. And made to run correctly. 



Dave Lazuka 



SIZE 

A 



DEC FORM NO 
DRA 108A 



CODE 

SP 



NUMBER 

TC08-0-16 

SHEET 3 



REV 

A 



OF 



7-14 



CONTINUATION SHEET 



TITLE 



TC08 & TC08N CHECKOUT PROCEDURE 



E. ELEVATED TEMPERATURE TESTING 

1. The control must run DECtrex 1 for ONE hour error free at 55 
centigrade. 

F. LIFE TESTING 

1. With all of the transports being shipped with the system, 
DECtrex 1 should be run for a minimum of ONE hour per 
transport. 

G. CLEANUP AND ADDITIONAL TESTS 

1. Checkout of the control is now complete . 

2 . Most DECtape systems are shipped in a cabinet and the system 
must be run after its installation in the cabinet before 
acceptance. 



Dave Lazuka 



SIZE 

A 



CODE 

SP 



NUMBER 

TC08-0-16 



REV 

A 



DEC FORM NO 
DRA 108A 



SHEET 



OF 



7-15 



I-0-S/Z9 SO a 

daawnN laooolazis 






THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE 
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY 
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION 



UNLESS OTHERWISE INDICATED; 
RESISTORS ARE 3K, I/4W, 5% 
NUMBERS IN PARENTHESIS ARE FOR 
FLEXPRINT CONNECTOR 2 

WHEN USING ONLY ONE FLEXPRINT 
CABLE, SIDE 2 MUST BE USED 

O ©INDICATES JUMPER 







ICO I FLEXPRINT 
CONNECTOR I 




FLEXPRINT 
CONNECTOR 2 



^/mf 



Wf^um 



PROD. 



DATE , 



mia 



TRANSISTOR & DIODE CONVERSION CHART 



EQUIPMENT 
CORPORATION 



"''CONNECTOR CARD 
INDICATOR PANEL G775 



CODE 

cs 



NUMBER 

G775-0-I 



PRINTED CIRCUIT REV. 



Ji/rr- jif ^-^r^ j^-is 



/>,, 



Txn 



SD a 

laooolazisl 



THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE 
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY. 
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION 



I 




UNLESS OTHERWISE INDICATEDi 
RESISTORS ARE l/4W,5% 
DIODES ARE D664 
TRANSISTORS ARE DEC3009B 



CHK'D 



>^ 



DATE 



JTRANSISTOR & DIODE CONVERSION CHART 
"dec 



EQUIPMENT 
CORPORATION 



TRANSPORT DETECTOR G879 



size code 
CS 

PRINTED CIRCUIT REV. 



NUMBER 

G879-0- 



3lST, SJ-HiH'lHiM' 



THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE 
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY. 
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION 



1-0-8889 SO a 

aaamiN laaoo azis 



I 



220 
D — W\/— 

R2 ^ ■^- 

220 
E — ^AA/— ♦- 



3 ['02 Vd4 



UNLESS OTHERWISE INDICATED 
CAPACITORS ARE lOOV 5% 
DIODES ARE D664 
RESISTORS ARE I/4W , 5% 
TRANSISTORS ARE DECI008-S 
EI,E2 ARE MCI709CG 
E3 IS DEC7400N 
PIN 7 ON E3 = GND 
PIN 14 ON E3 = + 5V 
R7 IS POT CERMET HELITRIM 76 PR 




N R L 



^:Ve^ 



?R0D 



TRANSISTOR & DIODE CONVERSION CHART 



EQUIPMENT 
CORPORATION 



MANCHESTER 
READER /WRITER G888 



SIZE CODE NUMBER 

B CS G888-0-I 



PRINTED CIRCUIT REV. 



DlsT- ?3-L(i M'SH ,^'5C ^ 



5 P'^*< 



i-o-2eoM so I g 

A3a. I aaawnN haoalazis 



THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE 
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY. 
COPYRIGHT 1968 BY DIGITAL EQUIPMENT CORPORATION 



5 CABLES OF 3 CONDUCTOR 
SHIELDED COAXIAL CABLE 

,yK 


















006000066006666000 
AA AB AC AD AE AF AH AJ AK AL AM AN AP AR AS AT AU AV 







OOO66666O6606 00000 

BA BB BC BD BE BF BH BJ BK BL »M BN BP BR BS BT BU BV 



note: 

ARE SPLIT LUGS 



PARTS LIST IS A-PL-W032-0-0 




JTRANSISTOR & DIODE CONVERSION CHART 
"dec 



EQUIPMENT 
CORPORATION 



CONNECTOR W032 



SIZE CODE NUMBER 

B I CS I W032-0- I 

PRINTED CIRCUIT REV^ [fl 



DIST 



\ |'/5^ |'/;-M31ll P(W 



iz 



THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE 
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY 
COPYRIGHT BY DIGITAL EQUIPMENT CORPORATION 



awoNQ ~ y I /. 



//SV /9C /A/ 
5 0/60 //Z 



NO 
O 




/3L^ 



9v /9c oo'r 

OO A/OT GA/Ci 



!5r Jieo ON OPTION / N^vooeL 

7I&-B 



c; 



/e/ 



T/ 



OI 



/P£^ £i^S/SA//9 r/ OA/ 



Cf}P /Spoo MFO /OV DC 



^es s SI zsuj,uJ.L. 



/=>9^T^ <L/ST 



y^MF^^^ef-o 7»//?£> 



D/ODS P/9CK D/<^ - 2 



z><FSC/e//=7'/<:?/V 



/009<?37' 



rSOO/Gt 



D-i//?-y/e-B -0 



/(Sossas 



//OS33Z 



/=^/P/?rs ^l/S7■ 



Wb/. 



Tt- 



a^rLH- 



DATE 



TRANSISTOR & DIODE CONVERSION CHART 



EQUIPMENT 
CORPORATION 



'CIRCUIT SCHEMATIC 
7I6B 



SIZE CODE 



B |cs I7I6-B 

PRINTED CIRCUIT REV. 






THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. 
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION 




UNLESS OTHERWISE INDICATED 
PIN 7 ON EACH IC= GND 
PIN 14 ON EACH 10= t5V 
IC'S ARE DEC 7400N 
CAPACITORS ARE ,01 MFD 
DIODES ARE 0662 
RESISTORS ARE I/4W 5% 
RESISTORS ARE 4.7K 
TRANSISTORS ARE DEC3009B 



2 Uajaia-^ 



DATE 



TRANSISTOR & DIODE CONVERSION CHART 



DEC3009e 



EQUIPMENT 
CORPOFJATION 



'BUS DATA INTERFACE 
MlOO 



i)lST /i-^,^'* ■f3<'^ 



V 






82 -I5V 




p 1 




Ulb 










k.1 


DI7 




Wl 


DI8 


" ' 








M 


DI9 


" 








U 


D20' 


M^ 










D2I 









JIMLESS OTHERWISE INDICATED; 
DIODES ARE D664 
RESISTORS ARE I. 5K | 1/4 W, 5% 
CAPACITORS ARE .01 MF0I00V20X 
TRANSISTORS ARE DEC3009B 
EI,E2,E3 ARE DEC74H40N 
E4 IS DEC7400N 
PIN 7 ON EACH IC = GND 
PIN 14 ON EACH IC = +5V 









TRANSISTOR 4 DIODE CONVERSION CHART 



DEVICE SELECTOR MI02 



C CS M 102-0- I 



IS- i->~'//it3t,Hie' 



IK 



? TEST AND MAINTENANCE F 



CO 




NOTES: 
PIN 7 ON EACH IC = GND 
PIN 14 ON EACH IC = +5V 




REFERENCE OESIONATION 



INTEGRATED CKT DEC7402N 



390 I/4W 5% CC 



DIODE D664 



CAP. e .eMFD S5V 20% STANT 
^AP' .01 MFD lOdv 20% DISC 

parts' list 



DESCRIPTION 



1909004 

isoaToo 



A-PL-M62 3-0-0 



PARTS LIST 



TRANSISTOR & DIODE CONVERSION CHART 



DE:C3009B 2N3009 



EQUIPMENT 
CORPORATION 



P/MK 



BUS DRIVER M623 



C CS M623-0-I 



wn 



pj^2 



\DIST.\ii-^\^J^jf\ 



I 
K) 

4v 



COPYRIGHT 19 69 8Y DIGITAL EQUIPMENT CORPORATION 




UNLESS OTHERWISE INDICATED; 

IC'S ARE DEC 7402 

PIN 7 ON EACH IC= GND 

PIN 14 ON EACH IC = + 5V 

CAPACITORS ARE 15 MMF 

RESISTORS ARE 5.6K, l/4W,S% 

TRANSISTORS ARE DEC3639B 



iCI4 ~CI5 ici6 ic 
OIMFD .OIMFD .OIMFD 01 



;:ci9 

OIMFD 



j^ tf S r/ iS y 



'HOD fl , J" DATE, 



TRANSISTOR 4 DIODE CONVERSION CHART 



DE«M3»B zmaM 



NEGATIVE BUS DRIVER 
M633 



j^ ///^x dTstTjjZ't^itt^^ 



iaTb]; 



I ! I-0-8Z2W ! SO I a 1 

I A3a I M3awnN J3Q03!37tSJ 



SCH.£MAT!C iS F'JRMSHED ONLY TCR TEST AND WAINTENANCE PUSPOSES. THE 
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDING:.','. 
COPYRIGHT Wt» BY DIGITAL EQUIPMENT CORPORATION 



MK BLK END H 



MK BLK MK H 



MK BLK SYNC H 




BC2,BTI,GND 



UNLESS OTHERWISE INDICATED: 

CAPACITORS ARE £)l MFD, IOOV,20% 

RESISTORS ARE I/4W, 5% 

PIN 7 ON EACH IC = GND 

PIN 14 ON EACH IC = +5V 

EI,E20 ARE DEC7400N 

E4 IS DEC7402N 

E7 IS DEC7450N 

EI9 IS DEC7453N 

E2,E3,E6,E9,EI2,Ei5,EI8,E2l ARE DEC7430N 

E5,E8,EI0,EII,EI3,EI4,EI6,EI7 ARE DEC7474N 



+ 5V 1 

GND 1 


1 1 1 1 I 1 1 1 i 1 

CI C2 C3 C4 C5 

1 1 1 II 1 1 1 1 1 


C6 Jc7 Jca 

- ] ]) 

1 * <> « 


C9 


CIO 
1 i 


CM 
1 i 


CI2 

1 i 


CI3 lci4 

1 1 1 1 


CIS 


CI6 


CI7 

1 1 


CIS 


CI9 Jc20 Jc2l C24^ 
1 (1 <) 1 1 



KC FORM NO. 



^l^J>Jt°^^ 



T^^2^y-/v 



^ 



TRANSISTOR & DIODE CONVERSION CHART 



dliigiiit a I 



EQUIPMENT 
CORPORATION 



MARK TRACK 
DECODER M228 



PRINTED CIRCUIT REV. M 



7-25 



i specifications, hersin, are the e 



i for the manufacture or sale of items without 



07.03031 fed,! 



LEGEHD 


NiUMBER 


V^B^\^T\ON 


TC<6©-<3i 


&0 VA.2: 


TC0 S- ;6^ 


SO VA.-Z. 



WIRE TABLE 



lTEMOESCR\PTlOH 
NO me] COLOR~ 



2^ BL^CK 



24- YEL 



COHUtCHON?. 



FRO^A 



SW-2 



c>NN-^ 



TO 



&0\£2_ 



E.<25SV\ 



R1.VAKRKS 




SECTION A-A 



S\N 




s< 



I 

lob 

B 




DEC FORM NO. 



jFIRST USED ON OPTION/ MODEL" 

TC0S 



DO NOT SCALE DRAWING 



UNLESS OTHERWISE SPECIFIED 

OlMEiaWN IN INCHES 

TOLERANCES 

DECIIULS FIUCTIONS M«SL£S 
£ .005 ± 1/M ± 0*30' 

nN«. SURFWE QUALITY / 



MATERIAL 

-^ 




SDSBDilD 



EQUIPMENT 
CORPORATION 



DECTAPE CONTROL 



SIZE CODE NUMBER 

D|Ua| TC08--0-0 

Msr- 1^1 I I II I I r"i 
I i 



7-27 



This dnnmiig and i ptci fl citloin. h«nin, an ttN pnp- 1 
•ftv of DigitaJ EauijiRMnt CoroMv^an and fhal nak hal 
reproduced or coptad or UMd in «tioi« or in part as! 
tha bans for tha mamilactura or tale of ItHiis wMMutl 



n NOTE: 

I TC08N ONLY 



VO BMB 03 (1 )L Pi 

I/O BM6 04 r 1 )L R1 



I/O BMB 0S ( 1 IL U! 



I/O BMB 07 t 1 IL M2 

I/O BMB 08 (0)L T2 



M102 
C04 




I/O BMB 03 ( t )H 
I/O BMB 04 (1 )H 
I/O BMB 05 ( IIH 
I/O BMB 0B ( HH 
I/O BMB 07 ( 1 IH 
I/O BMB 08 r0)H 
+3V C08U1 H 
+3V C08U1 H 



D2 


1 ^ 


E2 


Ml 03 
C04 


F2 


H2 


J2 






K2 


"U2 
+3V 


L2 
N2 



M103 
C04 



RSTfi L 
HI RSTn H 



+3V D10U1 H Dl 



RQr 171C f ! IH ri 



Ml 03 
C04 



C1 CSTfl H 



n xsin L 

El XSTR H 



LDMF H B1 



, O 
D 1 

MF00 
M206 

on 



+3V D10U1_H_K2 



C 0. 



BRC 07 f 1 IH E2 



01 PWR CLR L 



MF01 

M206 

Dll 



C 



BflC 08 M IH Jl 



MF02 

M206 

Dll 



C 







D 1 




H1„ 








WC 




- 


M20S 


XSTH H 


N1 


Dl! 
C 







f 



N M12t 
C08 



WCO L ^Rl 



I J2^ N M60 



I/O TS03 H 
<-3V C08U1 H Jl 




I/O BWCO L 


F1 




3V C08U1 H 


CI 


M101 
C01 









lOP 1 H P2 



TC08N ONLY 
I/O BMB 03 ( l.lL 



I/O BMB 04 I 1 )L Ri 

I/O BMB 05 ( 1 )L Si 

I/O BMB 06 C 1 IL Ul 



I/O BMB 07 C 1 )L M2 

I/O BMB 08 ( 1 IL T2 



Ml 02 
005 



lOP 2 H R2 



J 



lOP 4 H S2 



I/O BMB 03 ( MH 
I/O BMB 04 ( UH 
I/O BMB 05 ( HH 
I/O BMB 06 ( IIH 
I/O BMB 07 f llH 
I/O BMB 08 ( llH 
+3V C08U1 H 
+3V C08U1 H 



Ml 03 
C05 



Ml 03 
005 



Bl DTSF L 
HI DTSF H 



Ml 03 
C05 



Dl RSTB L 
Ct RSTB H 



Ml 03 
C05 



A 



Fl LDMF L 
El LDMF H 






I/O B-BRK (0)L 




■1M101 


\ El 


B-BRK H 


R2 






S2 


MG27 
B10 


+3V C08U1 H 


/ 




T2 




U2 









B-BRK H _M1 
T3 H 



LI BMB TO DTB H 



|U2 
+3V C08U1 




I/O B-RUN C0)L 



+3V C08U1 H CI 



M101 
C01 



Bl B-RUN ( 1 )H 



I/O PWR CLR H HI 
■>-3V C08U1 H Jl 



R SOFKH 10/2/69 



D LRZUKH 10/6/69 



TC08-00gB2 IB 



K COTE 12-9-69 



''l/1r', ij r?^-7^ 



M103 
C05 



Kl PWR ClR L 




DTF (1 )L 
R2 PWR CLR H 




ENI ( 1 )H 


HI 




\ Nl 


Jl 


M113 
H12 


) 


PI 




y 








DTSF H 


Rl 


M113 
R12 



Kl »)T RQ L 



SI SKP RQ L 



LDMF L P2 
XSTH L R2 



L2 XSHD H 



V2 B-BRK ( 1 )L 




P2 SH ST-B H 




-HDDR RCC H 




BDIDDSD 



I EQUIPMENT 
CORPORATION 



TtTLE 

I/O CONTROL 



SIZE CODE NUMBER 

BS TC08-0-1 



REV. 

C 



II I I I I I TTT 



7-29 



I This drawing and spedflcabora, hwiin, an tha prop- 
arty of Digital Equlpmant Cofporation and shall not be 
r^producad or copiad or usad In aihola or ki part as 
ittio basis for tha manufactaira cr lala of itwm wHtMut 
writtan panniasion. 



BnC 00 ( UH 



r 



USR 00 
M207 
B07 



_BRC 05 f 1 )H 
SI 



FR 02 

M207 

B07 



K2 



3V fi09U1 ri 


T2 






S! 


M161 




S2 


fl07 









USR 01 (1 )H U2 

USR 02 f nn VI 



RT 
^2" 



LI 
T2~ 



D1 
^2~ 



07 L 
07 H 
0G L 
06 H 
05 L 
05 K 
04 L 
04 H 
03 L 
03 H 
02 L 
02 H 
01 L 
01 H 
00 L 
00 H 



M117 
R09 



BRC 01 ( IIH 



BRC 02 ( IIH 



USR 01 
M207 
B07 



USR 021 
M207 
B07 



BRC 0S n IH 



BRC 07 r HH 



FR 01 

M207 

B07 



K2 



FR 02 
M207 

cm? 



RI 



3V D09U1 H 


T2 


M161 
D07 , 


2 
22 

2' 
2^ 


9 
8 

7 
G 
5 

4 

3 
2 

1 



-'R2 






SI 






kpT 






S2 














SE L 
SE H 










UI 
1 


^H1 


URTM L 
WRTM H 




-^Ml 
-^M2 


WRITE RLL L 
WRITE RLL H 


FR 


01 ( 1 


IH T V2 


^F1 


WRITE DRTR L 






WRITE DRTR H 


FR 


02 ( llH U2 

03 t HH VI 


-^ Nl 
"'n2 


RERD RLL L 
RERD ALL H 


FR 


-* J2 


READ DRTR L 
READ DRTR H 




^E2 
-^02 


SERRCH L 
SERRCH H 
MOVE L 
MOVE H 









TC08-00001 



R SQFKA 10/2/69 



: D LRZUKR 10/S/63 



NR TC08-00002 1 B ' 


K COTE 


I LhZUKR 


; r-'^ ;, ; TC08-00004 ! C 


1 \r^ .^'//f-w r£^-?' . 



_BRC 03 ( 1 IH 
N2 



MR00 

M207 

B07 



K2 TO SIR L 





BRC 08 f IJH 




F2 




H2 


J 1 








D2 


FR 03 

M207 

C07 












E2 


K 


J2 









M121 
009 

UI +3V D09U1 H 



+3V 812 U1H 



X SA DY H l2 



BRC 04 (IIH 



r 



MR01 

M207 

C07 



-J K — « 
O 



BMR00 

M20S 

B14 



K2 



+3V 312 UIH 



— ^BMR01 

M20S 

B14 



WRTM L H2 

FR 03 ( 1 )L J2 

READ DRTR L L2 

■iRITE DRTR L ri2 



BRC 

r ^^ 


9 f 1 )H 


L1 


J 1 

ENI 
M207 
C07 

K 




HI 






Jl 


Ml 









CSTA L L2 
PWR CLR L M2 



-RUN I 1 )H N2 

TO STR L P2 

=C + ES L R2 




Ml 13 \ N2 
R10 




T WRHE OK L 



W005 
B23 



M502 
A22 



02 WRITE OK H 




K2 WRTM + FR03 H 



K2 RD + WD H 




PI TO STA L 



SI M-STOP L 





( 1 )L 
(0JL 


Al 
CI 


-c 


1 


0^ 


^ W005 1 
B23 1 

02 1 




BMR 01 


M633 K 
fl23 F\ 


T GO L 




:a 


V W005 ' 
323 1 

E2 1 






31 


-c 












■\ 1 

M633 W 

R23 H^ 


T STOP L 


BMR 01 


.t 


. W005 1 
323 ' 

H2 ' 






(0)L 


Ft ^ 






1 




BMR00 


MS33 VJ 
R23 H 






C 1 )L 


Jt 




T FWD L 




\ 


, W005 1 
323 1 

j2 I 






HI 


<: 






1 






Me33 \J 
A23 H 


T REV L 


BMR00 


.i 


, W005 ' 
B23 1 

K2 i 






:;lr l 


M1 ^ 










PWR 


MS33 Vu 
A23 /^ 

y i 






01 L 


PI 




T PWR CLR 




si 


, W005 1 
B23 1 

M2 1 






Nl 


-c 






1 






M633 W- 

A23 yi 


T 01 L 




H2i 


, W005 1 
B23 1 

N2 1 






02 L 


02 








1 






A23 Pr 
y 1 






03 L 


F2 


-G 
< 

k: 

k: 
■< 

-<; 
-<: 

-<: 

-c 
-c 

-<: 
-c 


T 02 L 




i 


> W005 ' 
323 1 

F2 1 






E2 






MS33 Vj. 
A23 /^ 


T 03 L 




N2I 


, W005 1 
323 1 

R2 1 






04 L 


K2 






r 






MS33 V>L 

A23y> 






05 L 


M2 


T 04 L 




i 


W005 1 
323 1 

S2 1 






L2 






1 






M633 kI 
R23 M" 


T 05 L 




i 


W005 ' 
323 1 

T2 1 






06 L 


R2 












MG33 W 
R23 /^ 






07 L 


T2 


T 06 L 




i 


W005 1 
323 1 

U2 1 






S2 












MG33 VvL 
R23 H" 

1 


T 07 L 




U2 

I 

V2I 


W005 ' 
B23 1 

V2 1 








R2 






MS33 VJ 






00 L 


T2 






S2 






"ii)* 


T 00 L 











DRN. DATE 

D.'ShEPARD G/24/6 3 



^l^^ERU 



fJ^lRZUKR 



S«V-f«'9>CA 



§*/?/ 



FIRST USED ON 

TC08 



OF 1 



EQUIPMENT 
CORPORATION 



TITLE 

'sThT. 



SCEICODEI NUMBER 

D BS TC08-0-2 



REV. 

C 



■I I I I I I i"rri 



7-31 






R2 TP0 XTLK DY L 



TM EN L K2 



SI TP00 R H 




Mi 13 
CIS 



U1 ^3V ClSUl H 



t3V 812Ui H 



niaD 



M401 PRR 
D15 8.33 US 



CK00 (0JH T2 
,E2 



Th EN H R2 
CK01 [0W S2 



-TM EN H Dl 



fRK (0jH El 



-TM EN H D2 
T TRK ( 1 )H E2 



TM EN H Ml 
;K01 ( IIH N1 



T TRK (0)L Ul 



WRTM H 

SWTM H 

-U + M DY H 


N2 
P2 


M115 V 
C12 h 


^ 










i ^ 


SWTM H LI [ 
^R EN 1 i IH Ml 


M113 
CIS 


-iMl 13 
J C'S 



U + M DY H ~~m^ ^ 



di 



SI TM EN H N1 




+3V D10U1 H Ml 



M307 

D14 



(BOTTOM POT.) 

70 US 



PI TM EN L 



H2 SP DY H 



+3V ClSUl H K2 



F2 SP DY L 



V2 S2 R2 P2 N2 |V1 |P1 



UTS t0)H P2 



T TRK ( 1 )H R2 



BfiC 00 ( 1 )L F1 

BRC 01 f ML HI 

BfiC 02 ! 1 IL ^Jl 
SfiC 03 ! i : 

BfiC 04 ( 1 )L K2 

+3V D10U1 H L2 



XSTR L K2 




<>-^. ,vl.J 



H? 



M-STOP L LI/ 



M307 
DM 



D2 pi 61 El Fl 



K1 U + M DY H 
. E2 U + M DY L 



REVISIONS 1 


CHK 


CHANGE NO. 


REV. 


NR 


TC08-a0P01 


R 




-;r en I \ )i J2 

->: -N ^ K2y jMl 15 
U^S ( 1 jL L2_>J CI 2 



M2 W <■ UTS H 



. R.SOFKR _1,2-2_-f;9_ 
i^LXH i3-5-SS 



CK01 
M208 



VI CK01 t0)H 



+ 3y B12U1 H k2 



+3V B12U' H Rl 



CK01 ( 1 IH P1 
Nl 



81 CK00 f 1 )H 



CK00 

M20S 

B14 



11 rwaa ! a i 



+3V B12U1 H K2 




El TO W L 



LI TO STATE L 



Om. [DATE 

D.SHEPRRD B/24/6:! 



B'^tfiZL 



^'tP 3E.> 



FIRST USED ON 

TC08 



SHEET 1 OF 1 



mm 



[EQUIPMENT 
CORPORATION 



•CODE 

BS 



NUMBER 

TC08-0-3 



REV. 

C 



7-33 



This drawing and speciflcationt, htnin, an the prop- 1 
erty of Digital Equipmant Cotporitioa aiid shaH not b* I 
[«pioducad or copied or usad in wfwia or in lurt a^l 
the basis for tiM manufactura cr nl« of itBfns ivittKHit! 
writtan pannisaion. j 



Ml 19 
OK 

V'l +3V D10U1 H 



Ml 17 
612 



f3V Diaul H K2 



+3V fl09Ul H K2 



WC ( 1 IL n2^ 
TO DF H L2 



OF 

n206 

01 1 



CLR DF L ^M2 



•r^ 



1 TO DTF H S2 



DTF 
H20e 
D1 1 



URITE ALL H S2 



CLR DTF L U2 



W-INH 

M20S 

R08 



WC C IIH Ml 
TP00 H Nl 



C01 (0)H PI 
MKT C0)H Rl 



MG27 V- 51 



U2 



MC00 

M206 

813 



MC01 

M20G 

B13 



[iC02 

M206 

B13 



ST REV CK f 1 )H 


ni 


nl 13 Vi ci 
C11 H 




MC01 (0)H 


B1 
D1 






DflTH ( I )L 
-WRITE DflTR L 


Ml 
Nl 
PI 
Rl 


ST FINAL ( 1 )H 


Ml 13 V, Fl 
Cll H 




MC01 ( 1 )H 


El 
Hi 










REFID DRTH H 


M113 V) '<1 
Cll H 




RD EN H 


Jl 


LI 



C00 ;0)H HI 

I Ml 13 
TP00 H Jl i BIS 




-TP01 H L2 



C01 
M20G 
B13 



+ 3V Fi09Ul H 




Rl 










U2 




























PI 


A 


SI 




12 


A 


V2 


MKT ( 1 )H 




D 1 

C00 
M20G 
B13 


D 1 

MKT 
M20G 
B13 




Ul 


VI 


MKT (0)H 


TP00 H 


Nl 




S2 

























Jl 1 TO DF H 



BLK IN SYNC H E2 



flODR ncc L 


-^^ 


^Ml 13 


PUR CLR L 


_U2^ 


J 608 




Ul CLR DF L 



FR 00 !01H Kl 

I TO DF h Ll 

URTM + FR03 H Ml 



Ml IS 
C12 



FR 00 (0)H 


PI 




RO + WD H 


Rl 


Ml IS 


ST CK 0P H 


SI 


C12 



WC (0)H 


T2 




FR 00 ( 1 JH 


Ui 


Ml IS 


WRTM + FR03 H 


V2 
D2 


C12 


RD + WD H 






FR 00 ( 1 )H 


E2 


Ml 17 
312 


WC {0)H 
ST CK 0P H 


F2 
H2 




P2 1 TO DTF H 



8-XSTfl H P2 
BHC 11 t0)H R2 



Ul CLR DTF L 



Bl ST CK 0P H 



MKT (0)H H2 



REVISIONS 


CHK 


CHANGE NO. 


REV. 


NR 


TCf18-00001 


fi 


R.SOr KR 10-2-69 


D-LRZUKR 10-S-S9 


^-- 


TC08-00005 : B 


■ : ■■/r'--. -/-/a 


■ - ■ - /'^ 


1 




. 


1 







K2 



DRTH f 1 JL 


LZr 


\ -- 


T FINRL ( 1 )L 


_M2^ 


-^Ml 13 
J Cll 


SYNC H 


D2 








£2 


MG27 

B10 


TP00 H 


F2 




H2 



N2 RD EN H 



J2 SYNC -P L 




SI BLK IN SYNC H 



m.. 



RRST USED ON 

TC08 



SHEET 1 OF 1 



SDSDQID 



lEQUIPMENT 
CORPORATION 



TITLE 

'flrgs 



SEEICODE 

6S 



NUMBER 

1008-0-^1 



7-35 



BLK IN SYNC 



WR EN (1 )H 
TP01 H 



TP00 H El 




C00 ( 1 )H L2 
C01 ( 1 )H M2 



Mm K_N2_ 
fll2 



C00 (0)H P2 I 

I MIU Vv-S2_ 
C01 (S)H R2 I R12 



COMP + SH H 02 



SH EN H E2 



FR 01 (0)H H2 



TP01 H J2 



Kl COMP + SH H 



I Ml 13 \ V2 -SH EN H M2^ „,,, 
U2 J R12 7 CiMlll 




MC01 (0)H Pj 

WRHE DfiTfl H R1 
ST REV CK ( 1 )H SI 



WC ( 1 )H Kl 



W-INH (0)H LI 
WRITE RLL H M1 



MKT ( UH L 



FR 01 (1 )H Ml 




UTS ( UH PI 



WRITE OK H Rl 




Ml WRITE OK + UTS H 



ST REV CK ( IIH 01 




TC08-00001 IR 



oflTR [ nn Fl 



N2 SH EN H 



MC00 [0)H T2 




El ST REV CK ( 1 )L ST CK C 1 )H J1 




READ DRTR L J2 

SEARCH L K2 

S2 L2 



F2 ST BLK MK (0)H 




M2 SYNC EN H 



HI DRTR (IIL ST FWRL t 1 )H L1 




M1 ST FINRL ( 1 )L ORTfl ( 1 )L 02 

ST PInRL ('i1L :Ti:^"627 > J2 ST DRTR H H2. 

+3V C15U1 H H2. 



C16 



MC02 ( 1 )H U2 
C01 ( 1 )H V2 



M115 
B1 1 



■^Mlll 
C17 



Kl SHIFT CK H 



ST DRTR H Rl 
WRITE DRTR H Bl 



DTF (0)H CI 



WRITE OK + UTS H _m 

WRITE ALL H _F 
W-INH (0)H HI 

DF (0)H _J1 
WRITE OK + UTS H Kl 

WRTM H Rl 

SWTM H Bl 

WRITE OK H CI 



L1 TO DTB L LI 




Ml TO DTB H 




PWR CLR L ^RI 




J2 ST DATA L 



ST IDLE (0)L K2^ .. 

— ^tJ Mill 
I C13 




L2 ST IDLE (0)H 



k Ml 13 
B08 

VI SWTM H P2 



' EXTERNRll 

I swncH I 



D.SHEPARD S/21/S9 

N.RHEflULT G/24/69 

D.LRZUKA G/24/69( 

D.LRZUKA 9/2/69 

F.LASKEY 9/2/69 

TC08 




D BS TC08-0-5 



7-37 



This dnwing and spedflcations, h«r«ln, an tha prop- 
erty of Digital Equipmont Cotpotatloo and iftu not ba 
rcproducwj or copiad or mad In wfnia or In part as 



+3V H03U1HK2 



n,< SLK STRRT L fll 

m DflTn L 

MK BLK END L 

MK FND L 01 > 




ST SLK riK C0)H 02 

ST IDLE (0;H £2 

-MOVE H F2 

H2 



M117 
fi09 



MKTK 

n20G 

fi08 



TO EF L ^N2 





PI 




O-^i- 




RERO DRTR H 
LPB NOT EQ 1 H 


LI 
Ml 




+3V fl09Ul HK2 
O 


Ul 




M113 ^ 
ni0 J 


N1 


1 

PAR 
K20S 
R08 

C 




-^ic 


Ml 11 




ST CK ( 1 )H 


Mn3 ^ 
010 J 










MC00 C0)H 


y 








SI 











TO EF L IRI 



BRC 10 (0)H D2 
B-XSTfl H E2 





PWR CLR L 


_H2^ 
_J2^ 


S ^ 


Ml 13 
fil0 


Am113 
J R10 



K2 TO EF H 




F2 TO EF L 



+3V q03U1 H D1 







D 1 


El 






MK END H 


CI 


END 
M206 




TP0S H 


31 


fl08 
C 








F1 







TO EF L ^fil 



K2 
TIM (1 )L L2 
END ( 1 )L M2 
SEL ( 1 )L N2 



ft 



TC03-00001 



R.SOrKR 10-2-69 



O.LRZUKfl 10-6-69 



■TC08-00005 IB 






''M 




PWR CLR L 


-av 


^M113 




-^ 


J R12 


^V^"' 


Dl r 


4 ^ 


^ 




■^ M113 


'^RR ( 1 )L 


^U 


J fil2 
7 ^ 



URTM H ,<2 
-SWTM H L 



-WRTM H M2 
SWTM 



+3V H09U1 H F2 



T SINGLE UNIT L T2 



C1__PC+_ESH_H2 



Fl EF II ]H 




J2 -WRITE OK H 



OF ( 1 )H P2 


M113 
R10 


>- 


>^ 






SH DTB H R2 


>113 




J ni0 


ST SLK MK (01H 


Ml 


/ _. 


Ml 17 V 
R09 J- 




ST IDLE (0)H 


Nl 




RD + UID H 
XSRD H 


PI 
Rl 











T2 XSH DY H 



?^F 



^?v6:i 

^?/G9 



,I=^SKEY 
RRST USED ON 

TC08 



SHEET 1 OF 1 



SDSDDSD 



EQUIPMENT 
CORPORATION 



TtTLE 

ERRORS 



SIZE CODE NUMBER 

D 8S TC08-0-6 



7-39 



7=^(?i nUMC i 





RDMK ( n.H 
















330 OHMSk 
\/'t S7. <^ 

+5VDC 




























































6 


DF2 




6 


CLl 






cS 


CK2 




O 


CM2 




1 
6 


DU2 




(S 


CT2 




(^ 


DE2 




A 


DV2 






o 


DJ2 




CS2 

DF1 


D 1 
W09 

C 






1 
W08 

C 








D 1 
W07 

C 






D 1 
W06 

C 






D 1 
W05 

C 






D 1 
W04 

C 






D 1 
W03 

C 






D 1 
W02 

C 








D 1 
W01 

C 
















































































TO W L 




o 

DH2 




9 




Y 




O 




O 




Y 

1 




O 




O 




y 




TP01 H 




1 






























ST CK C 1) H 
SHIFT CK H DR2 



CN2 ST IDLE ( 1 )H 



W01 C 1 )L 
UI05 ( 1 )L 



CK1 W01-W05 H 



M228 
CIS 
D18 



DS2 MK BLK SYNC H 



MARK TRACK DECODE 



D BS TC08-0-7 



7-41 



BMB TO DTB H 



BfiB 09 ( HH 




SH EN H Rl 



-SH EN H CI 



WB00 t0)H D1 




D 1 

Kji UB00 
M20S 

C14 



D1 +3V CiSUl H 



BMB TO DTB H PI 



BMB 10 ( IIH Rl 



+3V C15U1 H 



iF2 +3V C15U1 H 



BMB TO DTB H D2 



BMB 11 ( 1 )H E2 




+3V C15U1 H 



D.SHEPflRD 6/24/69 
N.RHERULT 6/24/S9 
D.LflZUKri 3/24/69 r 



, ^ 1 












D.LflZUKn 
F.Ln5KEY 

TC08 

1 


9/2/69 
9/2/69 

D B5 

1 


TC08-0-8 


fl 






i 










i 




I 












8 


7 


G 


5 


4 


3 


2 




1 




i 



7-43 




7-45 



This drawing and spedfrcations. htrein. ara tfia prop- 
erty of Digital Equipment Corporation and shall not be 
reproduced or copied or used In wtiole or in part as 
the basis for tfie maniffactur* or sal* of itanis without 



BflC 00 (1 )L Rly 



Ml ■ 
B0S 



BfiC 01 C HL Dl- 



BfiC 02 MIL Fl, 



BflC 03 ( 1 )L Jl, 



BRC 04 r 1 )L LI 



BRC 05 tl )L _N1 



BflC 06 MIL Rl/ 



BflC 07 ( nL VI, 



SnC 08 f 1 )L CI, 



REVISIONS J 


CHK 




CHANGE NO. 


REV. 






TC08-00005 


fl 


.:' '\- .;ir'^-'. 




-'', . . '' , <- 


/¥- ?C 


\ ' 1 


' 




1 










1 



Bl BflC 00 ( IIH 




El BflC 01 (1 )H 



HI BflC 02 ( 1 )H 



Kl BflC 03 ( 1 )H 



Ml BflC 04 ( 1 )H 




PI BflC 05 ( ni- 






si BflC 0S ( 1 )H 



Ul BflC 07 ( UH 



02 BflC 08 ( UH 



^. 



BRC 09 ( IIL Z2r 



BflC 10 f UL _HZ, 



BflC 1 1 (1 )L KZy 





BMB 00 ( 1 )L fll. 



8MB 01 i nL Dl 



SMB 02 M IL 



BMB 03 tnL J1, 



BMB 04 ( nL LI, 



BMB 05 ( IIL N1, 



F2 BflC 09 ( nH 



J2 BflC 10 (1 IH 



BMB 0G ! nL Rl 




L2 BflC 11 ( IJH 




Bl BMB 00 ( IJH 



BMB 07 (IIL VI, 



BMB 08 ( nL C1, 



BMB 09 ( llL E2, 




Ml 1 1 
C0e 



Ml 1 1 
C0G 




El BMB 01 ( nH 



BMB 10 ( nL H2,- 






H1 BMB 02 ! nH 



Kl BMB 03 ( nH 



Ml BMB 04 (IJH 



BMB 11 >' IIL K2,. 



PI BMB 05 ( nn 



G821 
fl01 


SI 


+5 SENSE 
5ND SENSE 

+5V 


G821 

B01 


SI 


+5V 


N2 


N2 


fl2 


R2 


Bl 


Bl 




CI 


Ci 




Dl 


Dl 




El 


El 




n 


Fl 


GND 


HI 


HI 


Jl 


Jl 
Kl 


Kl 


LI 


LI 


Ml 


GND 


Ml 


N1 
PI 


N1 


PI 


Rl 


Rl 


C2 


C2 


D2 


02 




H2 


H2 




J2 
K2 
L2 

Tl 


GND 
GND 


J2 




K2 




L2 




T1 


GND 







si BMB 0G ( nn 



ui BMB 07 ( nn 




02 BMB 08 (IJH 



F2 BMB 09 ( nn 



_J2 SMB 10(1 )H 



L2 BMB 11 ( IIH 



CK00 (1 JL N2 

TM EN H R2 

CK00 (IIH P2, 



WB00 ( 1 )H N2 
TM EN H R2 
WB00 ( 1 )L P2, 



WB02 (IIH N2 

NR EN ( 1 IH R2 

WB02 ( 1 IL P2 



WB0! ( 1 )H N2 

WR EN (1 )H R2 

W801 ( 1 )L P2, 



NB00 


( 1 
(1 


)H 

)H 


N2 


WR EN 


R2 


WB00 


( 1 


)L 


-^2c 




U2 RDMK ( 1 )H 
V2 RDMK (IIL 



2 ROD 02 ; \ 
V2 ROD 02 ( 1 



u2 RDU 01 ( nj 
V2 RDD 01 (1)1 



U2 RDD 00 (1)1 
V2 RDD 00 ( nl ^ 



^.■^ftE 



m. 



^^r 



■LflSKEY 
FIRST USED ON 

C08 

SCALE 

SHEET 1 OF 



Wh 



BBIflflSD 



lEQUIPMENT 
CORPORATION 



I/O BIS INVTS READ WRITE R^PS 



SIZE CODE NUMBER REV. 

BS TC08-0-10 fl 



7-47 



This drawinc and spacScatkms, hvrabi, h» tha prap- 
•rty of Digitat Equipment CorporatlMi and ihaH not b* 
npntducad or copM or wad in whola or in part aa 



DTB 00 ( 1 IL Rl 



DTB 01 
DTB 02 



DTB 03 
DTB 04 



DTB 05 
DTB 06 



DTB 07 
DTB 08 



f 1 )L_ 
( 1 )L 



[ 1 )L_ 
[ 1 )L 



DTB 10 
B-BRK 



( 1 jL_ 
( 1 )L 



^^-T-C 



M623 
3S2 



— c 



MS23 
802 ^ 



M623 

B02 \ 



M623 
802^ 



M623 
B02 



Uf 



M623 
302 



MG23 
802 



MG23 
B02 



MS23 
802 



k: 



-c 



MG23 
802 



11623 
B02 



DTB 11 ( UL S2 



MG23 
802 



SEARCH L K2 



r 



MS23 
805 



MG23 
805 



Dl D8 00 (1 )L 



El DB 01 (1 )L 



Kl DB 02 ( 1 )L 



L! DB 03 ( 1 )L 



Rl D8 04 (1 )L 



SI DB 05 (ML 



H2 D3 06 (1 )L 



J2 DB 07 (1 )L 



N2 DB 08 (1 IL 



P2 DB 09 (1 IL 



V2 DB 11 ( 1 )L 



USR 00 ( IIL Rl 



USR 01 ( 1 )L_ 
USR 02 t HL 



MR00 t IJL. 
MR01 ( 1 )L 



FR 00 ( 1 jL_ 
FR 01 f 1 JL 



FR 02 (1 )L_ 
FR 03 C 1 )L 



M623 
C\ _ y-j B03 



MG23 
803 



M623 
B03 



"-c 



MG23 
803 



M623 
B03 



k: 



^^ 



MG23 
803 



M623 
803 



c j °"^y 



k; 



MG23 
803 



n MS23 
H2 ^ 803 



4 



MG23 Vv_f2_ IM 09 



DF ( HL HI 



N2 I/O +1 TO CH INH L 



M623 
B05 



MG23 
SI r- 805 



MG23 
805 



TO flC L HI 



MG23 
B05 



Dl I/O BRK RQ L 



:i I/O INT RQ L 



Kl I/O SKP RQ L 



LI I/O TO HC L 



EF f 1 iL Rl 



-<rzr\. 



MKTK r 1 )L_ 
END I. 1 IL 



TIM C 1 )L_ 
MF00 ( 1 )L 



MF01 ( 1 ■;l_ 

MF02 ( 1 )L 



MG23 
804 



M623 
804 



MG23 
804 



MS23 
B04 



^ MG23 
_NJ pj 804 



^1 riS23 
M2 ^J 804 



MG23 
804 



MF00 ( IIL Ml 



-c 



FR 01 f0)L 



MS23 
B05 



M 



M623 
N1 J 805 



M623 
805 



k: 



MG23 
805 



iri laio L 



El IM 01 L 



Kl IM 02 L 



LI IM 03 L 



Rl IM 04 L 



M623 W H2 IM 0G L 



MG23 K J2 IM 07 L 






P2 IM 11 L 



Rl ER 00 L 



SI ER 01 L 



H2 ER 02 L 



I/O BMB 00 t IIH 



I/O BMB 01 f UN 



I/O BMB 02 ( llH 



I/O BMB 03 c nn 



I/O BMB 04 (IIH 



I/O BMB 05 ( 1 )H 



I/O BMB 06 (IIH 



I/O BMB 07 ( HH 



I/O BMB 08 r llH 



I/O BMB 09 ( llH 



I/O BMB 10 f UH 



I/O BMB 11 ( nn 



T/O RDDR P.CC (01H_ 
J2 I/O DRTR IN H 



"^ 



Ml0i 
C02 



M101 
C02 



M101 
C02 



M101 
C02 



M101 
C02 



M10 
C02 



M101 
C02 



~^ 



M101 
C02 



M101 
CI I C02 



M101 
C02 



M101 
C02 



M101 
C02 



M101 
C02 



81 BMB 00 ( 1 IL 



El BMB 01 ( 1 IL 



HI BMB 02 ( 1 )L 



Kl BMB 03 ( 1 IL 



Ml BMB 04 ( UL 



PI BMB 05 ( 1 )L 



BMB 06 ( 1 )L 



Ul BMB 07 U )L 



F2 BMB 08 ( HL 



T/O BRC 00 ( 1 ?H Rl 



I/O BRC 01 ( 1 )H 



I/O BRC 02 M IH 



I/O BRC 03 f llH 



I/O BRC 04 C IIH 



I/O BRC 05 (IIH 



I/O BRC 06 t IIH 



I/O BRC 07 f IJH 



I/O BRC 08 f 1 )H 



I/O BRC 09 ( 1 )H 



I/O BRC 10 CI )H 



L2 BMB 10 ( IIL 



N2 BMB 11 ( 1 )L 



i/'o BRC 11 ( nn 



M101 K 81 BRC 00 C1)L 
003 



M101 V s El BRC 01 !.\)L 
C03 



Ml 01 V n hi BRC 02 CI )L 
C03 



Ml 01 K Kl BRC 03 C 1 )L 
C03 



Ml 01 V s Ml BRC 04 C 1 )L 
C03 



Ml 01 V , PI BRC 05 C HL 



Ml 01 V x SI BRC 06 C 1 )L 
C03 



Ml 01 W Ul BRC 07 C 1 )L 
C03 



Ml 01 K F2 BRC 08 C 1 )L 
CI I C03 



H2J ^ 

M101 V n J2 BRC 09 C 1 )L 
C03 



M101 K L2 BRC 10 C 1 )L 
C03 



M101 W N2 BRC 11 C UL 
C03 



V2 -RDDR RCC L 



NR TC08- 



: R SQFKR 10-2-69 



i D LRZUKR 



.'/ i TC08-000g4 I 3 



ORN. 

D.SHEPRRD 



DATE 
3/24/6 ) 



SHEET 1 OF 1 



EQUIPMENT 
CORPORATION 



TITLE 

'l/O BUS DRIVE/RECIEVE 



NUMBER 

TC08-0-n 



"^- 1 I I I I I I I I I 



7-49 




M903 
H02 




CHK 


CHANGE NO. 


REV. 


NR 


TC08-00001 


R 


R SOrKR 10-2-63 1 




3 LQZUKR 



M903 
004 



M903 
R04 



F2 
H2 



L2: 

M2j 

_P2\ 

^2| 

S2i 



M903 
D04 



_1H 01 L 
IM 02 L 



_IM 03 L 
TM 04 L 



_IM 05 L 
IM 08 L 



I/O INT RQ L 



I/O B-RUN (0JL 



CI 

Dl : IM 01 L 
El : IM 02 L 



LI I IM 05 
Ml , IM 0B 



PI j IM 07 L 



"R2l 



D2i IM 09 L 



I/O SKP RQ 



H2( I/O INT RQ L 



P2: I/O TO flC L 



S2i I/O B-RUN [0)L 





M903 
H05 




M903 
R0B 


DB 00 [ 1 IL 






fll 






Rl 






Bl 








. Bl 




CI 






CI 


DB 01 f 1 IL 






' Dl 




Dl 






El 




° El 


03 02 ( IlL 




Fl 




Fl 


DB 03 CI )L 






HI 




HI 




J1 i 




J 1 


j_DB 04 ! 1 IL 




Kl 




Kl 


DB 05 f 1 IL 






LI 




Ll 




Mil 


Ml 


^OB 0B ; 1 IL 




Nl 






Nl 


DB 07 (1 1L 






PI 




PI 




' R1 






Rl 


_DB 08 ( UL 






SI 


" SI 






' Tl 






Tl 






Ul 








Ul 






VH 


VI 












" 






- 


M903 
H05 


- 


y 


M903 
R0G 






= 02 






fl2 






B2 




B2 








. C2 








C2 


D8 09 (1 IL 






D2 






D2 




. E2 
F2 


^ 


E2 
F2 


DB 10 ( UL 
DB 1 1 I llL 






H2 








H2 




J2 




' J2 








K2 
. 1-2 


^I/D BRK RQ L 
_l/0 DFlTR IN H 
_I/0 3-BRK ;0)L 




K2 






L2 


I/O +1 TO Cfl If 


t 




M2 
- N2 




M2 


IH L-^ 


° N2 


_I/0 BWCO L 

ER 02 L 
^Efl 01 L 

^Ffl 00 L 
DB 00 t 1 )L 




P2 
'_ R2 


P2 
1 R2 






S2 




I/O HDDR HOC (0)H 


1 S2 
T2 
U2 




. U2 








. ^2 




V2 








^ 






M903 
D05 


- 


M903 
D0G 






fll 




fll 






Bl 








Bl 




01 






CI 


DB 01 f 1 )L 






Dl 




Dl 




: El 


El 


rOB 02 ( 1 )L 




Fl 




Fl 


r 

DB 03 ! 1 IL 






HI 




HI 




" Jl: 


Jl 
Kl 


_DB 04 ( lIL 

DB 05 ( 1 )L 

DB 0D f i IL 




Kl 








LI 




Ll 
Mi 




Ml 




' Nl 




Nl 


08 07 (1 IL 






P! 






PI 




° Rl 






Rl 


DB 08 ( n L 






SI 


1 SI 

Tl 




° Tl 








Ul 








Ul 






VI 


: 


VI 


















- 


1903 
D05 


_L 


M903 
D06 






R2 






fl2 






62 




B2 








C2 








C2 


D6 09 f 1 IL 






D2 






D2 




° E2 




I/O BRK RQ L 


' E2 


08 10 ( llL 




. ^2 




. (^2 


DB 11 I liL 






H2 




H2 




J2 






J2 








y ^2 




K2 




* L2 




L2 


_I/0 +1 TO OR » 
_I/0 BWCO L 
ER 02 L 


1 




M2 
r N2 


_I/0 DRTR IN H 
_I/0 B-BRK (0)L 


■ , M2 
1 N2 


H L-^ 


1— ^ P2 
L_ R2 


■ P2 
i - R2 






S2 




I/O RDDR flCC (01H 




S2 




T2 






T2 


ER 01 L 




U2 








U2 


ER 00 L 






„ ^2 




V2 

















"i0?3 






R24 






fl2 
B2 
C2 


T 


GO L 


D2 


~T 


STOP L 


E2 
F2 


FWD L 
REV L 


H2! T 
J2^ 


PWR CLR L 


K2 

L2 


T 
T 


SINGLE UNIT 
WRITE OK L 


M2 
N2 


T 
T 


01 L 

02 L 


P2 


T 


03 L 


R2 


T 


04 L 


S2 


T 


05 L 


T2| T 
U2' T 


08 L 
07 L 


V2 


r 


00 L 



M91S 
R25 



USR 00 ( 1 iH 

'Bi i u sR 01 f n H 

Cl' USR 02 M IH 
Dl; M R00 I 1 IH 
El MR0I I 1 IH 



,Hlj FR 01 ( 1 

]J1' F R 02 I 1 

,Ki: FR 03 I 1 

Ll lNI ( 1 Iri 



Ml ; 



NK EF n iH I 
PI MKTK f llH ■^ 


Rl END 


I 1 IH 


SI SEL 
Tl PAR 
Ur TIM 


f 1 IH 
( 1 IH 
f 1 JH 


VI ■ MF0e 


1 1 IH 


M91S 




fl25 




fl2i 0TB 


00 1 1 IH 


82 DTB 
:C2; DTB 


01 f 1 )H 


D2i DTB 


03 [ llH 


"'E2: DTB 
F2: DTB 


04 ( 1 IH 

05 [ 1 IH 


H2 DTB 


06 ( 1 IH 


J2 DTB 


07 C 1 IH 


K2. DTB 


08 f 1 IH 


'l2: DTB 


03 ( 1 IH 


M2j DTB 


10 f llH 


N2: DTB 


11 ( llH 


P2| WB02 
R2i WB01 


( 1 IH 
( 1 )H 


'S2r~WB02 


( 1 )H 


T2: LPB 
U2 LPB 
V2 LPB 


00 ( 1 )H 

01 ( llH 

02 ( 1 )H 


M9ie 




R28 




flit MF01 


r 1 )H 


:Bi| Mr02 


' ' ]H 


,C1j DTF 


( 1 IH 


Dll 




El DF C 1 IH 
"fi , WR EN M )H 

Hi WC ( 1 )H 

Jl UTS ( 1 )H 
"K1 ST BlK MK ! ] ]n 

Ll ST REV CK ( I IH 

Ml DflTH ( I )H 


Nl ST F 


INRL ; 1 IH 


„P1, ST CK ( 1 )H 
Rl ■ ST IDLE ( 1 IH 


SI MC00 
Tl MC31 


( 1 )H 

r 1 )H 


Uli MC02 


( 1 )H 



M9i6 
fl28 



_LPB 03 r llH 
_LPB 04 r llH 
LPB 05 ( llH 



E2; C00 ( 


iH 


1 


F2 001 ( 


)H 




H2 MKT f 


)H 




J2 W01 ( 


)H 




K2' W02 ( 
L2^ W03 ( 
M2i W04 ( 
N2 W05 ( 


)H 

)H 
)H 
)H 




P2: W0G ( 
R2| W07 ( 


)H 
)H 




__S2: W08 t 

12. W09 ( 


IH 
)H 





..V2i SWTM H 



"a 



DRN. 

D.SHEPRRD 



PROJ. ENG, 
D.LflZUKR 



DATE 

S/24/f 



EQUIPMENT 
CORPORATION 



TITLE 

'l/O eUS-^CONNECTORS 



7-51 



■Hy of Diiiui iw ipiw nt Cnm i m n MM <m « _ 
' - i»H<«r»w< la «Mi « k pM« 



I I •«» I 



K3-0-^6eeODIpV{D| 2 I 

i3awnM IJOoaBasI I 




■SEE DETfllL /? 



ST 



:^ 



z <S + 



S3 



8 9 K) Ctl 



vr 



^ 14 is i6 i> 18 <S^ +^ ^i ^s ^4 ^i ^fe c^ H- 1> ^ ^rig 



8 9 10 <1 + -^ 14 IS 16 17 18 Cj^ 



^ 22 23 24 25 26 ^ -j- :^ 30 31 ^ 



5fr 



19 REF 






— +-- 



NOTES: 

I. CONNECTIONS ON ITEMS ifl f # 2 TO BE 
SOLDERED AND LOCATED AT MINIMUM 
PRACTICAL HEIGHT ABOVE BOARD. 

2. ALL CONN BLOCKS TO BE GROUNDED 
TO GND LUGS AS SHOWN. 

a USE YELLOW WIREOTEM*^.) FOR 
MACHINE WRAPPED i BLUE WIRE 
(ITEM its) FOR HAND WRAPPED WIRING. 



SEE noTt^i 



S£E nOTE^3 




DETAIL A 

8 PLACES 
SEE NOTE*'2 



first used on option/ 
model: ' 

TC08 



yNLESS OTHERWISE SPEaFlED 
UNLESS OTHERWISE SPECIRED 

DWENtMN IN INCHCt 

TOLERANCES 

imam I FMcnoNt unasi 

^jm ± l/M s 0*30- 

nNM. MMMCI OUMJTr </ 



HATEMM. 



-f /- 



-t /- 




digital 



EQUIPMENT 
CORPORATION 



WIRED ASSY 
TC^S 



SIZE CODE 

DAD 



NUMBER 

ZQQ&394-0-Q 



•I ' -rn 

1 



7-53 



! ! b 



erty cf Digita! Equiprrre-it Corporatio 
reproduced or copied or used in w 



DEC TAPE CONTROL 

D-UA-TC08-0-0 

60H2 



DEC TAPE CONTROl 

D-UA-TC08-A-0 

50H2 



© 



® 



WIRED ASSY 

TC08 

D-AD-7006394-0-0 



dy 



IND POWER SUPPLY 
T16 50 4 60 HZ 
D-UA-7 16-0-0 



POWER CONTROL 

832-F 
D-UA-832-F-0 



H91I MTG PANEL 
D-AD-540449 1-0-0 



0- 



® 



INDICATOR PANEL 

ASSY (TC08) 

D-AD-700633 1-5-0 



© 



POWER CONTROL 

832-E 
D-UA-832-E-0 



783 POWER 

SUPPLY 

D-UA-7 83-0-0 



LIGHT BOARD i 

CABLE ASSY 

E-IA-70064O9-5-O 



1943 CASTING PLUS 

PINS 
D-AD-53D2483-0-D 



(§- 



PERIPHERAL 
ETCH BOARD ASSY 
E-IA-5408458-5-0 



INLAY 
(TCD8) 
D-iA-7 407228-6-O 



FIND 
NO. 



djstribution 
pn;l assy 

DAD -7005909-0-0 



FAN HOUSING 

ASSY 
E-AD-7005 474-0-0 



POWER SUPPLY 
TYPE 783A 
D-UA-783A-0-I 




DESCRIPTION 



DEC TAPE CONTROL 
DEC TAPE CONTROL 
DEC TAPE CONTROL (PL) 
CABLE, DUAL MYLAR M903-(2) W031 



WIRED ASSY TC08 

WIRED ASSY TC08 (PL) 
LOGIC FRAME CECALS 



H911 MTG PANEL 
H9II MTG PANEL (PL) 



1943 CASTING PLUS PINS 

1943 CASTING PLUS PINS (PL) 
1943 FRAME CASTING 



IND POWER SUPPLY 716 

IND POWER SUPPLY 716 (PL) 



POWER CONTROL 832-F 

POWER CONTROL 332-F (PL) 



INDICATOR PANEL ASSY (TC08) 

iNDICA:iOR PANEL ASSY (TC08) (PL) 



LIGHT BOARD & CABLE ASSY 

PERIPHERAL ETCH BOARD ASSY 



POWER CONTROL 832-E 

POWER CONTROL 832-E (PL) 



783 POWER SUPPLY 

783 POWER SUPPLY (PL) 



POWER SUPPLY TYPE 783A 

POWER SUPPLY TYPE 783A (PL) 



INDICATOR PANEL (TC08) 
IND PANEL SILK SCREEN 
IND PANEL SILK SCREEN 

FAN HOUSING ASSY 

FAN HOUSING ASSY (PL) 

DISTRIBUTION PANEL ASSi 
DIST PANEL ASSY (PLj 



PART NO. 



D-IIA-TC08-0-D 
n_ij»_TCQo_i_n 

A-PL-TC08-0-0 
D-UA-BC08C-0-0 



D-AD-7006394-0-0 
A-P I -7 006 394-0-0 
A-OC-740637 1-0-0 



D-AD-540449 1-0-0 
A-PL-540449WO-0 



D-AD-5302483-0-0 
A-PL-5302483-0-0 
E-MD-1 202885-0-0 



D-UA-7 16-0-0 
A-P L -7 16-0-0 



D-UA-S32-F-0 
A-PL-832-F-0 



D-AD-700633I-5-O 
C-PL-700633i-5-O 



E-IA-70064O9-5-O 



E-IA-540845&-5-O 



0-UA-832-E-0 
A-PL-332-E-0 



D-UA-7 83-0-1 
A-PL-783-0-1 



D-UA-783A-0-1 
A-PI-733A-0-1 



E-IA-7407228 5 
C-SS-7407228-O-6 
C-SS-7407228^(^-2 

E-AD-7005474-0-C 
A-PL-7005474-0-C 

A- pL-idixhod^o-o 



^gOQ|3Z'.S! 



FIND 
NO. 



DEC TAPE CONT 

I '0 CONTROL 

STATUS 'A' 

TP GEN 

FLAjSS 

CONTROL 

ERRORS 

MARK TRACK DECODE 

DTB'WB 

LPa 

I'O BIS INVTS-IND DVRS 

|/0 BUS DRIVE RECEIVE 

ro BUS CONNECTORS 

MODULE UTILIZATION LIST 

MODULE UTILIZATION LIST 

WIRE LIST TCtlB 

CHECKOUT PROCEDURE 

TIMING DIAGRAM 



WIRED ASSY TC08 

WIRED ASSY TC08 (PL) 



A-ML-TC08-0 

A-ML-TCOS— A 

D-BS-TC88-0-1 

D-BS-TC08-0-2 

D-BS-TC08-0-3 

D-BS-TC08-0-4 

D-eS-TC08-0-5 

D-BS-TC08-0-6 

D-BS-TC08-0-7 

D-BS-TC08-0-8 

3-BS-TC08-0-9 

D-BS-TC08-0-I0 

D-BS-TC08-0-n 

D-BS-TC08-0- 12 

K-MU-TC08-0-13 

K-PL-TC08-0-13 

K-WL-TCOa-0-14 

A-SP-TC08-0-I6 

D-TD-TC08-0-I7 



D-AD-7006394-0-0 
A-PL-7006394-0-0 



PROD CUSI F C 



FIRST USED ON OPTION/ MODEL 

TC0 8 



DO NOT SCALE DRAWING 



UNLESS OTHERV¥ISE SPECIFIED 

DIMENSION IN INCHES 

TOLERANCES 

DECIMALS FRACTIONS ANGLES 
± .005 * 1/64 - 0*30' 

FINAL SUBFACE QUALITY / 



■V — ^ 



-h-i- 



DEC FORM NO 




:CD 



IQ 



7-55 



This drawing and spccificationi, Iwnin, are ttia prot 
crty of Digital Equipment Corpontion and shall not b 
reproduced or copied or used in wtiole or in part I 
Oasis for ttie manufacture or sale of items withot 



a39WnN • J 3Q03J 3ZISi j 



REV END MK 



IINTER BLK i 

192) ;SY'^25 (199); 



FWD BLK MKJREV GUARD MKj LOCK 

26 1 32 ; 



MK JREV PCC MKIREV final MKIREV PRE FINAL MkI DATA 



MKl DATA 



MKIPRE FINAL MKI FINAL 



MK 1 PCC 



IP 



10 



MKIREV LOCK MK| GUARD 

I 73 lb) 



- A S 



I. I.I . I. i. I. I.I .1.1 .1.1. I i III 



rr-i 



il0ii 10) 110111 1101011 1 il0| 110101011 i0l0l0l0l(^lil0)0|0|0|^ 



1 [ [ 1 i 1 i gTT 



DATA 



DATA 



DATA 



DATA 



-HaTT 



QATA 






IP I j 
'P 0A il 

IP 1 I 

IP lA ~^ 



' l \ ' : ' l 'l ' l 'i 'l i | ^1 ' l ^1 'l ' l l| ' l l| 'l 'l 'l 'l 'i ' l l | ' l 'l 'l 'l 'l ' l ' i 'l ' l 'l ' l 'l ' l ^1 'l 'l 'i ' l ' i 'l 'l 'l 'l 'l l| ' l 'l ' l ' l 'l ' l ' l ' l 'l ' l ' l ' l 'i 'l 'l 'l l| l| 'l ' l ' l l | 'l ' l ' l 'l ' l ' l ' , 'l ' i ' l ' ■ ' l ' l 'l 'l ' . ' l ' l ' l 'l 'l 'l 'l ' i 'l 'i 'l ' : S ■! 



(READ) 
(READ) 
( READ) 
(READ) 

(WRITE) 
(WRITE) 
(WRITE) 
f WRITE) 
(WRITE) 
(WRITE) 
(WRITE) 



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